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Class Information
Number: 257/48
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Test or calibration structure
Description: Subject matter in which structures are provided on active solid-state devices to permit or facilitate the measurement, test, or calibration of the characteristics of the devices.










Patents under this class:

Patent Number Title Of Patent Date Issued
5949090 MOS TEG structure Sep. 7, 1999
5949129 Wafer comprising optoelectronic circuits and method of verifying this wafer Sep. 7, 1999
5949134 Tape carrier and tape carrier device using the same Sep. 7, 1999
5949136 High performance debug I/O Sep. 7, 1999
5942766 Article and method for in-process testing of RF products Aug. 24, 1999
5942805 Fiducial for aligning an integrated circuit die Aug. 24, 1999
5940680 Method for manufacturing known good die array having solder bumps Aug. 17, 1999
5936260 Semiconductor reliability test chip Aug. 10, 1999
5936311 Integrated circuit alignment marks distributed throughout a surface metal line Aug. 10, 1999
5932891 Semiconductor device with test terminal and IC socket Aug. 3, 1999
5930166 Semiconductor memory device with triple metal layer Jul. 27, 1999
5923047 Semiconductor die having sacrificial bond pads for die test Jul. 13, 1999
5923048 Semiconductor integrated circuit device with test element Jul. 13, 1999
5920067 Monocrystalline test and reference structures, and use for calibrating instruments Jul. 6, 1999
5920081 Structure of a bond pad to prevent testing probe pin contamination Jul. 6, 1999
5917197 Integrated multi-layer test pads Jun. 29, 1999
5912502 Wafer having a plurality of IC chips having different sizes formed thereon Jun. 15, 1999
5909034 Electronic device for testing bonding wire integrity Jun. 1, 1999
5907764 In-line detection and assessment of net charge in PECVD silicon dioxide (oxide) layers May. 25, 1999
5905384 Method for testing semiconductor element May. 18, 1999
5903011 Semiconductor device having monitor pattern formed therein May. 11, 1999
5903012 Process variation monitor for integrated circuits May. 11, 1999
5903489 Semiconductor memory device having a monitoring pattern May. 11, 1999
5900643 Integrated circuit chip structure for improved packaging May. 4, 1999
5900644 Test site and a method of monitoring via etch depths for semiconductor devices May. 4, 1999
5900645 Semiconductor device and method of testing the same May. 4, 1999
5898186 Reduced terminal testing system Apr. 27, 1999
5894161 Interconnect with pressure sensing mechanism for testing semiconductor wafers Apr. 13, 1999
5892245 Ball grid array package emulator Apr. 6, 1999
5889410 Floating gate interlevel defect monitor and method Mar. 30, 1999
5886362 Method of reflowing solder bumps after probe test Mar. 23, 1999
5886363 Semiconductor device and pattern including varying transistor patterns for evaluating characteristics Mar. 23, 1999
5886539 Communication within an integrated circuit by data serialization through a metal plane Mar. 23, 1999
5880016 Method for adjusting the circuit characteristic of a circuit body by cutting wires external to the circuit body Mar. 9, 1999
5877033 System for detection of unsoldered components Mar. 2, 1999
5869877 Methods and apparatus for detecting pattern dependent charging on a workpiece in a plasma processing system Feb. 9, 1999
5864501 Test pattern structure for endurance test of a flash memory device Jan. 26, 1999
5861634 Charge collector structure for detecting radiation induced charge during integrated circuit processing Jan. 19, 1999
5859442 Circuit and method for configuring a redundant bond pad for probing a semiconductor Jan. 12, 1999
5850088 Teg for carrier lifetime evaluation Dec. 15, 1998
5838022 Evaluating the lifetime and reliability of a TFT in a stress test using gate voltage and temperature measurements Nov. 17, 1998
5838023 Ancillary pads for on-circuit array probing composed of I/O and test pads Nov. 17, 1998
5834795 Test pattern for measuring line width of electrode and method for measuring the same Nov. 10, 1998
5831280 Device and method for programming a logic level within an integrated circuit using multiple mask layers Nov. 3, 1998
5831446 Process monitor test chip and methodology Nov. 3, 1998
5828081 Integrated semiconductor device Oct. 27, 1998
5825076 Integrated circuit non-etch technique for forming vias in a semiconductor wafer and a semiconductor wafer having vias formed therein using non-etch technique Oct. 20, 1998
5818251 Apparatus and method for testing the connections between an integrated circuit and a printed circuit board Oct. 6, 1998
5801394 Structure for wiring reliability evaluation test and semiconductor device having the same Sep. 1, 1998
5793117 Semiconductor device and method of fabricating the same Aug. 11, 1998











 
 
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