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Class Information
Number: 257/390
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Field effect device > Having insulated electrode (e.g., mosfet, mos diode) > Insulated gate field effect transistor in integrated circuit > Matrix or array of field effect transistors (e.g., array of fets only some of which are completed, or structure for mask programmed read-only memory (rom))
Description: Subject matter wherein the integrated circuit contains a two dimensional array of IGFETs, only some of which are completed devices, or the integrated circuit contains structure for a mask programmed read-only memory device.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6737714 |
FET having a gate electrode of a honeycomb structure |
May. 18, 2004 |
| 6737711 |
Semiconductor device with bit lines formed via diffusion over word lines |
May. 18, 2004 |
| 6734508 |
Mask ROM, and fabrication method thereof |
May. 11, 2004 |
| 6730973 |
Semiconductor device |
May. 4, 2004 |
| 6730952 |
Semiconductor device including ion implantion compensation region in cell array region |
May. 4, 2004 |
| 6727557 |
Semiconductor device having well tap provided in memory cell |
Apr. 27, 2004 |
| 6720629 |
Structure of a memory device with buried bit line |
Apr. 13, 2004 |
| 6720210 |
Mask ROM structure and manufacturing method thereof |
Apr. 13, 2004 |
| 6717222 |
Three-dimensional memory |
Apr. 6, 2004 |
| 6713821 |
Structure of a mask ROM device |
Mar. 30, 2004 |
| 6713886 |
Semiconductor device |
Mar. 30, 2004 |
| 6710414 |
Surface geometry for a MOS-gated device that allows the manufacture of dice having different sizes |
Mar. 23, 2004 |
| 6703669 |
Semiconductor device having serially connected memory cell transistors provided between two current terminals |
Mar. 9, 2004 |
| 6700165 |
Semiconductor structure with the common source line |
Mar. 2, 2004 |
| 6700168 |
Layout structure and method of a column path of a semiconductor memory device |
Mar. 2, 2004 |
| 6690073 |
Semiconductor integrated circuit making use of standard cells |
Feb. 10, 2004 |
| 6690058 |
Self-aligned multi-bit flash memory cell and its contactless flash memory array |
Feb. 10, 2004 |
| 6683342 |
Memory structure and method for manufacturing the same |
Jan. 27, 2004 |
| 6680501 |
Semiconductor device |
Jan. 20, 2004 |
| 6674105 |
Semiconductor memory device and method of forming the same |
Jan. 6, 2004 |
| 6674132 |
Memory cell and production method |
Jan. 6, 2004 |
| 6674133 |
Twin bit cell flash memory device |
Jan. 6, 2004 |
| 6674137 |
Semiconductor device and its manufacturing method |
Jan. 6, 2004 |
| 6671198 |
Semiconductor device |
Dec. 30, 2003 |
| 6670713 |
Method for forming conductors in semiconductor devices |
Dec. 30, 2003 |
| 6664164 |
UV-programmed P-type Mask ROM and fabrication thereof |
Dec. 16, 2003 |
| 6661061 |
Integrated circuit with differing gate oxide thickness |
Dec. 9, 2003 |
| 6653692 |
Double access path mask ROM cell structure |
Nov. 25, 2003 |
| 6653691 |
Radio frequency (RF) power devices having faraday shield layers therein |
Nov. 25, 2003 |
| 6653733 |
Conductors in semiconductor devices |
Nov. 25, 2003 |
| 6649945 |
Wiring layout to weaken an electric field generated between the lines exposed to a high voltage |
Nov. 18, 2003 |
| 6649972 |
Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
Nov. 18, 2003 |
| 6646312 |
Semiconductor memory device with bit lines having reduced cross-talk |
Nov. 11, 2003 |
| 6646301 |
Floating gate semiconductor device |
Nov. 11, 2003 |
| 6642611 |
Storage apparatus, card type storage apparatus, and electronic apparatus |
Nov. 4, 2003 |
| RE38296 |
Semiconductor memory device with recessed array region |
Nov. 4, 2003 |
| 6642587 |
High density ROM architecture |
Nov. 4, 2003 |
| 6642586 |
Semiconductor memory capable of being driven at low voltage and its manufacture method |
Nov. 4, 2003 |
| 6639287 |
Semiconductor integrated circuit device |
Oct. 28, 2003 |
| 6635943 |
Method and system for reducing charge gain and charge loss in interlayer dielectric formation |
Oct. 21, 2003 |
| 6635935 |
Semiconductor device cell having regularly sized and arranged features |
Oct. 21, 2003 |
| 6627962 |
Semiconductor memory |
Sep. 30, 2003 |
| 6624485 |
Three-dimensional, mask-programmed read only memory |
Sep. 23, 2003 |
| 6624484 |
IGFET and tuning circuit |
Sep. 23, 2003 |
| 6621130 |
Semiconductor device and an electronic device |
Sep. 16, 2003 |
| 6621129 |
MROM memory cell structure for storing multi level bit information |
Sep. 16, 2003 |
| 6617633 |
Vertical read-only memory and fabrication thereof |
Sep. 9, 2003 |
| 6614080 |
Mask programmed ROM inviolable by reverse engineering inspections and method of fabrication |
Sep. 2, 2003 |
| 6613661 |
Process for fabricating secure integrated circuit |
Sep. 2, 2003 |
| 6602749 |
Capacitor under bitline (CUB) memory cell structure with reduced parasitic capacitance |
Aug. 5, 2003 |
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