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Class Information
Number: 257/390
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Field effect device > Having insulated electrode (e.g., mosfet, mos diode) > Insulated gate field effect transistor in integrated circuit > Matrix or array of field effect transistors (e.g., array of fets only some of which are completed, or structure for mask programmed read-only memory (rom))
Description: Subject matter wherein the integrated circuit contains a two dimensional array of IGFETs, only some of which are completed devices, or the integrated circuit contains structure for a mask programmed read-only memory device.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 4940934 |
Method of electrically testing active matrix substrate |
Jul. 10, 1990 |
| 4933736 |
Programmable read-only memory |
Jun. 12, 1990 |
| 4931946 |
Programmable tiles |
Jun. 5, 1990 |
| 4902638 |
Thin film transistor, method of repairing the thin film transistor and display apparatus having the thin film transistor |
Feb. 20, 1990 |
| 4903111 |
Integrated circuit device |
Feb. 20, 1990 |
| 4896295 |
Eprom memory cell with two symmetrical half-cells and separate floating gates |
Jan. 23, 1990 |
| 4825273 |
Semiconductor integrated circuit device |
Apr. 25, 1989 |
| 4816887 |
CMOS gate array with orthagonal gates |
Mar. 28, 1989 |
| 4801983 |
Schottky diode formed on MOSFET drain |
Jan. 31, 1989 |
| 4780753 |
Semiconductor integrated circuit device |
Oct. 25, 1988 |
| 4771327 |
Master-slice integrated circuit having an improved arrangement of transistor elements for simplified wirings |
Sep. 13, 1988 |
| 4764798 |
Master slice IC having n and p channel transistors |
Aug. 16, 1988 |
| 4760560 |
Random access memory with resistance to crystal lattice memory errors |
Jul. 26, 1988 |
| 4758986 |
Single transistor cell for electrically-erasable programmable read-only memory and array thereof |
Jul. 19, 1988 |
| 4755864 |
Semiconductor read only memory device with selectively present mask layer |
Jul. 5, 1988 |
| 4748492 |
Read only memory |
May. 31, 1988 |
| 4745307 |
Semiconductor integrated circuit with a programmable logic array |
May. 17, 1988 |
| 4742019 |
Method for forming aligned interconnections between logic stages |
May. 3, 1988 |
| 4737835 |
Read only memory semiconductor device |
Apr. 12, 1988 |
| 4734887 |
Erasable programmable read only memory (EPROM) device and a process to fabricate thereof |
Mar. 29, 1988 |
| 4724531 |
Gate array with bidirectional symmetry |
Feb. 9, 1988 |
| 4716308 |
MOS pull-up or pull-down logic circuit having equalized discharge time delays and layout avoiding crossovers |
Dec. 29, 1987 |
| 4709351 |
Semiconductor memory device having an improved wiring and decoder arrangement to decrease wiring delay |
Nov. 24, 1987 |
| 4701777 |
Gate array type semiconductor integrated circuit device |
Oct. 20, 1987 |
| 4679171 |
MOS/CMOS memory cell |
Jul. 7, 1987 |
| 4651190 |
Semiconductor integrated circuit |
Mar. 17, 1987 |
| 4641279 |
Semiconductor memory device having a dummy cell and a memory cell which is twice the size of the dummy cell |
Feb. 3, 1987 |
| 4618945 |
Semiconductor memory device |
Oct. 21, 1986 |
| 4608748 |
Method of manufacturing a memory FET with shorted source and drain region |
Sep. 2, 1986 |
| RE32236 |
One device field effect transistor (FET) AC stable random access memory (RAM) array |
Aug. 26, 1986 |
| 4591891 |
Post-metal electron beam programmable MOS read only memory |
May. 27, 1986 |
| 4586238 |
Method of manufacturing field-effect transistors utilizing self-aligned techniques |
May. 6, 1986 |
| 4566022 |
Flexible/compressed array macro design |
Jan. 21, 1986 |
| 4554643 |
Electrically erasable programmable MNOS read only memory |
Nov. 19, 1985 |
| 4551705 |
Programmable integrated circuit AC resistor network |
Nov. 5, 1985 |
| 4541076 |
Dual port CMOS random access memory |
Sep. 10, 1985 |
| 4536944 |
Method of making ROM/PLA semiconductor device by late stage personalization |
Aug. 27, 1985 |
| 4493056 |
RAM Utilizing offset contact regions for increased storage capacitance |
Jan. 8, 1985 |
| 4476478 |
Semiconductor read only memory and method of making the same |
Oct. 9, 1984 |
| 4476547 |
DRAM with interleaved folded bit lines |
Oct. 9, 1984 |
| 4409724 |
Method of fabricating display with semiconductor circuits on monolithic structure and flat panel display produced thereby |
Oct. 18, 1983 |
| 4406049 |
Very high density cells comprising a ROM and method of manufacturing same |
Sep. 27, 1983 |
| 4404581 |
ROM With redundant ROM cells employing a highly resistive polysilicon film for programming the cells |
Sep. 13, 1983 |
| 4402044 |
Microprocessor with strip layout of busses, ALU and registers |
Aug. 30, 1983 |
| 4398207 |
MOS Digital-to-analog converter with resistor chain using compensating "dummy" metal contacts |
Aug. 9, 1983 |
| 4384345 |
Read-only memory device |
May. 17, 1983 |
| 4380866 |
Method of programming ROM by offset masking of selected gates |
Apr. 26, 1983 |
| 4352031 |
Precharge circuit |
Sep. 28, 1982 |
| 4336647 |
Method of making implant programmable N-channel read only memory |
Jun. 29, 1982 |
| 4336604 |
Monolithic static memory cell |
Jun. 22, 1982 |
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