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Class Information
Number: 257/390
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Field effect device > Having insulated electrode (e.g., mosfet, mos diode) > Insulated gate field effect transistor in integrated circuit > Matrix or array of field effect transistors (e.g., array of fets only some of which are completed, or structure for mask programmed read-only memory (rom))
Description: Subject matter wherein the integrated circuit contains a two dimensional array of IGFETs, only some of which are completed devices, or the integrated circuit contains structure for a mask programmed read-only memory device.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 5754467 |
Semiconductor integrated circuit device and process for manufacturing the same |
May. 19, 1998 |
| 5751038 |
Electrically erasable and programmable read only memory (EEPROM) having multiple overlapping metallization layers |
May. 12, 1998 |
| 5751031 |
Memory and other integrated circuitry having a conductive interconnect line pitch of less than 0.6 micron |
May. 12, 1998 |
| 5751040 |
Self-aligned source/drain mask ROM memory cell using trench etched channel |
May. 12, 1998 |
| 5747856 |
Vertical channel masked ROM memory cell with epitaxy |
May. 5, 1998 |
| 5742078 |
Integrated circuit SRAM cell layouts |
Apr. 21, 1998 |
| 5736751 |
Field effect transistor having thick source and drain regions |
Apr. 7, 1998 |
| 5736771 |
Mask ROM cell structure with multi-level data selection by code |
Apr. 7, 1998 |
| 5734188 |
Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same |
Mar. 31, 1998 |
| 5734177 |
Semiconductor device, active-matrix substrate and method for fabricating the same |
Mar. 31, 1998 |
| 5731606 |
Reliable edge cell array design |
Mar. 24, 1998 |
| 5721698 |
Read only memory device and manufacturing method |
Feb. 24, 1998 |
| 5703744 |
Circuit substrate including anodization control means |
Dec. 30, 1997 |
| 5698876 |
Memory standard cell macro for semiconductor device |
Dec. 16, 1997 |
| 5698879 |
Nonvolatile semiconductor memory device |
Dec. 16, 1997 |
| 5691574 |
Semiconductor device capable of high speed operation and being integrated with high density |
Nov. 25, 1997 |
| 5691551 |
Semiconductor memory device |
Nov. 25, 1997 |
| 5691562 |
Through glass ROM code implant to reduce product delivering time |
Nov. 25, 1997 |
| 5682323 |
System and method for performing optical proximity correction on macrocell libraries |
Oct. 28, 1997 |
| 5672891 |
Semiconductor memory apparatus for a dynamic RAM and method for manufacturing the same |
Sep. 30, 1997 |
| 5665995 |
Post passivation programmed mask ROM |
Sep. 9, 1997 |
| 5663589 |
Current regulating semiconductor integrated circuit device and fabrication method of the same |
Sep. 2, 1997 |
| 5654572 |
Static random access memory device |
Aug. 5, 1997 |
| 5654563 |
Microelectronic integrated circuit including triangular semiconductor "or" g |
Aug. 5, 1997 |
| 5654577 |
Semiconductor integrated circuit device |
Aug. 5, 1997 |
| 5654576 |
Post-titanium nitride mask ROM programming method and device manufactured thereby |
Aug. 5, 1997 |
| 5650956 |
Current amplification type mask-ROM |
Jul. 22, 1997 |
| 5648672 |
Semiconductor device with outer diffusion layer |
Jul. 15, 1997 |
| 5646429 |
Segmented non-volatile memory array having multiple sources |
Jul. 8, 1997 |
| 5646436 |
Read only memory (ROM) device produced by self-aligned implantation |
Jul. 8, 1997 |
| 5644154 |
MOS read-only semiconductor memory with selected source/drain regions spaced away from edges of overlying gate electrode regions and method therefor |
Jul. 1, 1997 |
| 5643816 |
High-density programmable read-only memory and the process for its fabrication |
Jul. 1, 1997 |
| 5637895 |
Non-volatile semiconductor memory device |
Jun. 10, 1997 |
| 5635748 |
NAND ROM with transistor strings located at trench bottoms as well as between trenches |
Jun. 3, 1997 |
| 5633519 |
Non-volatile floating gate semiconductor device |
May. 27, 1997 |
| 5631486 |
Read-only-memory having both bipolar and channel transistors |
May. 20, 1997 |
| 5631484 |
Method of manufacturing a semiconductor device and termination structure |
May. 20, 1997 |
| 5631481 |
Flat-cell mask ROM integrated circuit |
May. 20, 1997 |
| 5621233 |
Electrically programmable read-only memory cell |
Apr. 15, 1997 |
| 5616946 |
VLSI ROM programmed by selective diode formation |
Apr. 1, 1997 |
| 5610429 |
Differential analog transistors constructed from digital transistors |
Mar. 11, 1997 |
| 5608241 |
Semiconductor device having a memory cell portion and a logic portion |
Mar. 4, 1997 |
| 5606193 |
DRAM and MROM cells with similar structure |
Feb. 25, 1997 |
| 5600163 |
Semiconductor element and semiconductor memory device using the same |
Feb. 4, 1997 |
| 5600171 |
Mask ROM device |
Feb. 4, 1997 |
| 5576573 |
Stacked CVD oxide architecture multi-state memory cell for mask read-only memories |
Nov. 19, 1996 |
| 5572056 |
High density ROM |
Nov. 5, 1996 |
| 5567970 |
Post metal mask ROM with thin glass dielectric layer formed over word lines |
Oct. 22, 1996 |
| 5563437 |
Semiconductor device having a large sense voltage |
Oct. 8, 1996 |
| 5561623 |
High speed DRAM with novel wiring structure |
Oct. 1, 1996 |
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