| |
 |
|
Class Information
Number: 257/390
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Field effect device > Having insulated electrode (e.g., mosfet, mos diode) > Insulated gate field effect transistor in integrated circuit > Matrix or array of field effect transistors (e.g., array of fets only some of which are completed, or structure for mask programmed read-only memory (rom))
Description: Subject matter wherein the integrated circuit contains a two dimensional array of IGFETs, only some of which are completed devices, or the integrated circuit contains structure for a mask programmed read-only memory device.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 5932909 |
Nonvolatile semiconductor memory device |
Aug. 3, 1999 |
| 5930663 |
Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering |
Jul. 27, 1999 |
| 5929494 |
Read only memory array and method of manufacturing the array |
Jul. 27, 1999 |
| 5925917 |
Contact programmable ROM and method of manufacturing the same |
Jul. 20, 1999 |
| 5920100 |
Multi-stage ROM structure |
Jul. 6, 1999 |
| 5920099 |
Read-only memory cell array and process for manufacturing it |
Jul. 6, 1999 |
| 5920101 |
Structure for making sub-lithographic images by the intersection of two spacers |
Jul. 6, 1999 |
| 5917224 |
Compact ROM matrix |
Jun. 29, 1999 |
| 5907167 |
Method and apparatus for providing ROM in an integrated circuit having update through single substance layer modification capability |
May. 25, 1999 |
| 5905289 |
Planarized metallurgy structure for a semiconductor and process of fabrication |
May. 18, 1999 |
| 5903036 |
Semiconductor device having MISFET SRAM cells in which active regions and gate electrodes are dimensioned for increasing storage node capacitances without increasing memory cell size |
May. 11, 1999 |
| 5894162 |
High density EPROM cell and process for fabricating same |
Apr. 13, 1999 |
| 5891781 |
Method for coding mask read-only memory |
Apr. 6, 1999 |
| 5883405 |
MOS transistor read-only memory device |
Mar. 16, 1999 |
| 5877537 |
Semiconductor device having first transistor rows with second transistor rows connected therebetween |
Mar. 2, 1999 |
| 5875138 |
Dynamic access memory equalizer circuits and methods therefor |
Feb. 23, 1999 |
| 5874746 |
TFT, method of making and matrix displays incorporating the TFT |
Feb. 23, 1999 |
| 5869863 |
memory having a trench type gate structure |
Feb. 9, 1999 |
| 5866928 |
Single digit line with cell contact interconnect |
Feb. 2, 1999 |
| 5864164 |
Multi-stage ROM structure and method for fabricating the same |
Jan. 26, 1999 |
| 5861635 |
Liquid crystal display including a coplanar line structure |
Jan. 19, 1999 |
| 5859460 |
Tri-state read-only memory device and method for fabricating the same |
Jan. 12, 1999 |
| 5852317 |
Method to reduce gate oxide damage due to non-uniform plasmas in read only memory arrays |
Dec. 22, 1998 |
| 5852318 |
Semiconductor device |
Dec. 22, 1998 |
| 5847441 |
Semiconductor junction antifuse circuit |
Dec. 8, 1998 |
| 5847426 |
Contactless flash EPROM using poly silicon isolation |
Dec. 8, 1998 |
| 5847420 |
Semiconductor integrated circuit having three wiring layers |
Dec. 8, 1998 |
| 5838046 |
Operating method for ROM array which minimizes band-to-band tunneling |
Nov. 17, 1998 |
| 5835409 |
Compact page-erasable EEPROM non-volatile memory |
Nov. 10, 1998 |
| 5834819 |
Semiconductor read-only memory device for permanent storage of multi-level coded data |
Nov. 10, 1998 |
| 5834818 |
Structure for making sub-lithographic images by the intersection of two spacers |
Nov. 10, 1998 |
| 5834851 |
SRAM having load transistor formed above driver transistor |
Nov. 10, 1998 |
| 5831314 |
Trench-shaped read-only memory and its method of fabrication |
Nov. 3, 1998 |
| 5825069 |
High-density semiconductor read-only memory device |
Oct. 20, 1998 |
| 5821592 |
Dynamic random access memory arrays and methods therefor |
Oct. 13, 1998 |
| 5821591 |
High density read only memory cell configuration and method for its production |
Oct. 13, 1998 |
| 5815433 |
Mask ROM device with gate insulation film based in pad oxide film and/or nitride film |
Sep. 29, 1998 |
| 5811862 |
Semiconductor device having a mask programmable memory and manufacturing method thereof |
Sep. 22, 1998 |
| 5804854 |
Memory cell array |
Sep. 8, 1998 |
| 5793086 |
NOR-type ROM with LDD cells and process of fabrication |
Aug. 11, 1998 |
| 5793087 |
Segmented non-volatile memory array having multiple sources |
Aug. 11, 1998 |
| 5789794 |
Fuse structure for an integrated circuit element |
Aug. 4, 1998 |
| 5783846 |
Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering |
Jul. 21, 1998 |
| 5777369 |
Bit-line pull-up circuit or static random access memory (SRAM) devices |
Jul. 7, 1998 |
| 5773867 |
Programmable hex-ROM with isolation transistor structure |
Jun. 30, 1998 |
| 5763925 |
ROM device having memory units arranged in three dimensions, and a method of making the same |
Jun. 9, 1998 |
| 5760454 |
Pattern form of an active region of a MOS type semiconductor device |
Jun. 2, 1998 |
| 5760452 |
Semiconductor memory and method of fabricating the same |
Jun. 2, 1998 |
| 5757054 |
Display unit |
May. 26, 1998 |
| 5754464 |
Mask ROM with field shield transistors functioning as memory cells and method of reading data thereof |
May. 19, 1998 |
|
|
|
