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Class Information
Number: 257/390
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Field effect device > Having insulated electrode (e.g., mosfet, mos diode) > Insulated gate field effect transistor in integrated circuit > Matrix or array of field effect transistors (e.g., array of fets only some of which are completed, or structure for mask programmed read-only memory (rom))
Description: Subject matter wherein the integrated circuit contains a two dimensional array of IGFETs, only some of which are completed devices, or the integrated circuit contains structure for a mask programmed read-only memory device.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6084794 |
High speed flat-cell mask ROM structure with select lines |
Jul. 4, 2000 |
| 6084275 |
Double coding mask read only memory (mask ROM) for minimizing band-to-band leakage |
Jul. 4, 2000 |
| 6084274 |
Semiconductor memory cell and its fabrication process |
Jul. 4, 2000 |
| 6081036 |
Semiconductor device |
Jun. 27, 2000 |
| 6078084 |
Semiconductor integrated circuit device |
Jun. 20, 2000 |
| 6072223 |
Circuit and method for a memory cell using reverse base current effect |
Jun. 6, 2000 |
| 6066866 |
Semiconductor device with alternating general-purpose functional regions and specific functional regions |
May. 23, 2000 |
| 6066870 |
Single digit line with cell contact interconnect |
May. 23, 2000 |
| 6064101 |
Read-only memory cell arrangement |
May. 16, 2000 |
| 6064100 |
Product for ROM components having a silicon controlled rectifier structure |
May. 16, 2000 |
| 6057573 |
Design for high density memory with relaxed metal pitch |
May. 2, 2000 |
| 6046482 |
Cell structure for mask ROM |
Apr. 4, 2000 |
| 6043543 |
Read-only memory cell configuration with trench MOS transistor and widened drain region |
Mar. 28, 2000 |
| 6040605 |
Semiconductor memory device |
Mar. 21, 2000 |
| 6040608 |
Field-effect transistor for one-time programmable nonvolatile memory element |
Mar. 21, 2000 |
| 6037225 |
Manufacturing method for mask ROM devices |
Mar. 14, 2000 |
| 6034384 |
Semiconductor memory device having memory cells similarly layouted and peripheral circuits symmetrically layouted in memory cell arrays |
Mar. 7, 2000 |
| 6034403 |
High density flat cell mask ROM |
Mar. 7, 2000 |
| 6028342 |
ROM diode and a method of making the same |
Feb. 22, 2000 |
| 6020241 |
Post metal code engineering for a ROM |
Feb. 1, 2000 |
| 6018186 |
Three-dimensional, deep-trench, high-density read-only memory (ROM) and its manufacturing method |
Jan. 25, 2000 |
| 6015995 |
ROM diode structure |
Jan. 18, 2000 |
| 6008522 |
Structure of buried bit line |
Dec. 28, 1999 |
| 6005270 |
Semiconductor nonvolatile memory device and method of production of same |
Dec. 21, 1999 |
| RE36440 |
Integrated circuit SRAM cell layouts |
Dec. 14, 1999 |
| RE36441 |
Semiconductor device and a method of manufacturing same |
Dec. 14, 1999 |
| 5998846 |
Layout structure of multi-use coupling capacitors in reducing ground bounces and replacing faulty logic components |
Dec. 7, 1999 |
| 5994745 |
ROM device having shaped gate electrodes and corresponding code implants |
Nov. 30, 1999 |
| 5994746 |
Memory cell configuration and method for its fabrication |
Nov. 30, 1999 |
| 5990527 |
Semiconductor read-only memory device and method of fabricating the same |
Nov. 23, 1999 |
| 5990525 |
ROM device structure comprised of ROM memory array cells, featuring concave channel regions |
Nov. 23, 1999 |
| 5990526 |
Memory device with a cell array in triple well, and related manufacturing process |
Nov. 23, 1999 |
| 5990529 |
Semiconductor memory device with impurity areas around trench structure |
Nov. 23, 1999 |
| 5977597 |
Layout structure of semiconductor memory with cells positioned in translated relation in first and second directions |
Nov. 2, 1999 |
| 5973374 |
Flash memory array having well contact structures |
Oct. 26, 1999 |
| 5973373 |
Read-only-memory cell arrangement using vertical MOS transistors and gate dielectrics of different thicknesses and method for its production |
Oct. 26, 1999 |
| 5969382 |
EPROM in high density CMOS having added substrate diffusion |
Oct. 19, 1999 |
| 5969379 |
Memory and other integrated circuitry having a conductive interconnect line pitch of less than 0.6 micron |
Oct. 19, 1999 |
| 5962903 |
Planarized plug-diode mask ROM structure |
Oct. 5, 1999 |
| 5962900 |
High-density diode-based read-only memory device |
Oct. 5, 1999 |
| 5959877 |
Mask ROM |
Sep. 28, 1999 |
| 5955769 |
Multiple stage ROM unit |
Sep. 21, 1999 |
| 5952698 |
Layout pattern for improved MOS device matching |
Sep. 14, 1999 |
| 5952697 |
Multiple storage planes Read Only Memory integrated circuit device |
Sep. 14, 1999 |
| 5949704 |
Stacked read-only memory |
Sep. 7, 1999 |
| 5949088 |
Intermediate SRAM array product and method of conditioning memory elements thereof |
Sep. 7, 1999 |
| 5945717 |
Segmented non-volatile memory array having multiple sources |
Aug. 31, 1999 |
| 5946558 |
Method of making ROM components |
Aug. 31, 1999 |
| 5942800 |
Stress buffered bond pad and method of making |
Aug. 24, 1999 |
| 5942786 |
Variable work function transistor high density mask ROM |
Aug. 24, 1999 |
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