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Class Information
Number: 257/382
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Field effect device > Having insulated electrode (e.g., mosfet, mos diode) > Insulated gate field effect transistor in integrated circuit > With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide)
Description: Subject matter wherein the device has an electrical contact to its source region or drain region wherein the contact is made of a refractory or platinum group metal, or of other material which has a melting point above that of the iron group of metals and which is resistant to heat (e.g., of polysilicon, tungsten or silicide).
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 5895948 |
Semiconductor device and fabrication process thereof |
Apr. 20, 1999 |
| 5894164 |
High voltage semiconductor device |
Apr. 13, 1999 |
| 5894160 |
Method of forming a landing pad structure in an integrated circuit |
Apr. 13, 1999 |
| 5894169 |
Low-leakage borderless contacts to doped regions |
Apr. 13, 1999 |
| 5880500 |
Semiconductor device and process and apparatus of fabricating the same |
Mar. 9, 1999 |
| 5877535 |
CMOS semiconductor device having dual-gate electrode construction and method of production of the same |
Mar. 2, 1999 |
| 5869864 |
Field effect controlled semiconductor component |
Feb. 9, 1999 |
| 5869874 |
Field effect transistor with barrier layer |
Feb. 9, 1999 |
| 5869875 |
Lateral diffused MOS transistor with trench source contact |
Feb. 9, 1999 |
| 5864155 |
Semiconductor array with self-adjusted contacts |
Jan. 26, 1999 |
| 5864160 |
Transistor device with reduced hot carrier injection effects |
Jan. 26, 1999 |
| 5856693 |
Semiconductor integrated circuit device containing MOS protection circuit |
Jan. 5, 1999 |
| 5847465 |
Contacts for semiconductor devices |
Dec. 8, 1998 |
| 5844284 |
Damage free buried contact using salicide technology |
Dec. 1, 1998 |
| 5844281 |
Semiconductor integrated circuit device with electrostatic protective function |
Dec. 1, 1998 |
| 5838050 |
Hexagon CMOS device |
Nov. 17, 1998 |
| 5838051 |
Tungsten policide contacts for semiconductor devices |
Nov. 17, 1998 |
| 5838068 |
Integrated circuitry with interconnection pillar |
Nov. 17, 1998 |
| 5834816 |
MOSFET having tapered gate electrode |
Nov. 10, 1998 |
| 5831899 |
Local interconnect structure and process for six-transistor SRAM cell |
Nov. 3, 1998 |
| 5831281 |
Thin film transistor |
Nov. 3, 1998 |
| 5831307 |
Silicon damage free process for double poly emitter and reverse MOS in BICMOS application |
Nov. 3, 1998 |
| 5821629 |
Buried structure SRAM cell and methods for fabrication |
Oct. 13, 1998 |
| 5818100 |
Product resulting from selective deposition of polysilicon over single crystal silicon substrate |
Oct. 6, 1998 |
| 5818091 |
Semiconductor device with selectively patterned connection pad layer for increasing a contact margin |
Oct. 6, 1998 |
| 5814862 |
Metallic source line and drain plug with self-aligned contacts for flash memory device |
Sep. 29, 1998 |
| 5814886 |
Semiconductor device having local connections formed by conductive plugs and method of making the same |
Sep. 29, 1998 |
| 5804862 |
Semiconductor device having contact hole open to impurity region coplanar with buried isolating region |
Sep. 8, 1998 |
| 5804846 |
Process for forming a self-aligned raised source/drain MOS device and device therefrom |
Sep. 8, 1998 |
| 5801421 |
Staggered contact placement on CMOS chip |
Sep. 1, 1998 |
| 5801424 |
MOSFET with reduced leakage current |
Sep. 1, 1998 |
| 5798554 |
MOS-technology power device integrated structure and manufacturing process thereof |
Aug. 25, 1998 |
| 5798549 |
Conductive layer overlaid self-aligned MOS-gated semiconductor devices |
Aug. 25, 1998 |
| 5793083 |
Method for designing shallow junction, salicided NMOS transistors with decreased electrostatic discharge sensitivity |
Aug. 11, 1998 |
| 5780896 |
Semiconductor device having shallow impurity region without short-circuit between gate electrode and source and drain regions and process of fabrication thereof |
Jul. 14, 1998 |
| 5777370 |
Trench isolation of field effect transistors |
Jul. 7, 1998 |
| 5767552 |
Structure for ESD protection in semiconductor chips |
Jun. 16, 1998 |
| 5763923 |
Compound PVD target material for semiconductor metallization |
Jun. 9, 1998 |
| 5760451 |
Raised source/drain with silicided contacts for semiconductor devices |
Jun. 2, 1998 |
| 5757050 |
Field effect transistor having contact layer of transistor gate electrode material |
May. 26, 1998 |
| 5751031 |
Memory and other integrated circuitry having a conductive interconnect line pitch of less than 0.6 micron |
May. 12, 1998 |
| 5744843 |
CMOS power device and method of construction and layout |
Apr. 28, 1998 |
| 5742088 |
Process having high tolerance to buried contact mask misalignment by using a PSG spacer |
Apr. 21, 1998 |
| 5739573 |
Semiconductor device with improved salicide structure and a method of manufacturing the same |
Apr. 14, 1998 |
| 5736770 |
Semiconductor device with conductive connecting layer and abutting insulator section made of oxide of same material |
Apr. 7, 1998 |
| 5734179 |
SRAM cell having single layer polysilicon thin film transistors |
Mar. 31, 1998 |
| 5729055 |
Integrated circuitry having a thin film polysilicon layer in ohmic contact with a conductive layer |
Mar. 17, 1998 |
| 5719429 |
High frequency/high output insulated gate semiconductor device with reduced and balanced gate resistance |
Feb. 17, 1998 |
| 5717242 |
Integrated circuit having local interconnect for reduing signal cross coupled noise |
Feb. 10, 1998 |
| 5710438 |
Semiconductor device with a silicide layer |
Jan. 20, 1998 |
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