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Class Information
Number: 257/371
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Field effect device > Having insulated electrode (e.g., mosfet, mos diode) > Insulated gate field effect transistor in integrated circuit > Complementary insulated gate field effect transistors > Complementary transistors in wells of opposite conductivity types more heavily doped than the substrate region in which they are formed, e.g., twin wells
Description: Subject matter wherein the complementary IGFETs are located in wells of semiconductor material with electrical conductivity opposite to that of the respective transistors and wherein the wells contain a higher concentration of dopant ions than the semiconductor substrate in which they are located (e.g., twin wells).


Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12

Patent Number Title Of Patent Date Issued
4764482 Method of fabricating an integrated circuit containing bipolar and MOS transistors Aug. 16, 1988
4762802 Method for preventing latchup in CMOS devices Aug. 9, 1988
4746219 Local interconnect May. 24, 1988
4728619 Field implant process for CMOS using germanium Mar. 1, 1988
4724221 High-speed, low-power-dissipation integrated circuits Feb. 9, 1988
4716451 Semiconductor device with internal gettering region Dec. 29, 1987
4697332 Method of making tri-well CMOS by self-aligned process Oct. 6, 1987
4696092 Method of making field-plate isolated CMOS devices Sep. 29, 1987
4695865 Integrated logic circuit having insulated gate field effect transistors Sep. 22, 1987
4673965 Uses for buried contacts in integrated circuits Jun. 16, 1987
4672416 Semiconductor device Jun. 9, 1987
4661202 Method of manufacturing semiconductor device Apr. 28, 1987
4604790 Method of fabricating integrated circuit structure having CMOS and bipolar devices Aug. 12, 1986
4599789 Process of making twin well VLSI CMOS Jul. 15, 1986
4584027 Twin well single mask CMOS process Apr. 22, 1986
4578859 Implant mask reversal process Apr. 1, 1986
4577390 Fabrication of polysilicon to polysilicon capacitors with a composite dielectric layer Mar. 25, 1986
4558508 Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step Dec. 17, 1985
4554726 CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well Nov. 26, 1985
4553315 N Contact compensation technique Nov. 19, 1985
4549340 Method of making CMOS semiconductor device using specially positioned, retained masks, and product formed thereby Oct. 29, 1985
4535529 Method of making semiconductor devices by forming an impurity adjusted epitaxial layer over out diffused buried layers having different lateral conductivity types Aug. 20, 1985
4525920 Method of making CMOS circuits by twin tub process and multiple implantations Jul. 2, 1985
4516316 Method of making improved twin wells for CMOS devices by controlling spatial separation May. 14, 1985
4507847 Method of making CMOS by twin-tub process integrated with a vertical bipolar transistor Apr. 2, 1985
4503451 Low resistance buried power bus for integrated circuits Mar. 5, 1985
4474624 Process for forming self-aligned complementary source/drain regions for MOS transistors Oct. 2, 1984
4470852 Method of making CMOS device and contacts therein by enhanced oxidation of selectively implanted regions Sep. 11, 1984
4468574 Dual gate CMOS transistor circuits having reduced electrode capacitance Aug. 28, 1984
4459741 Method for producing VLSI complementary MOS field effect transistor circuits Jul. 17, 1984
4442591 High-voltage CMOS process Apr. 17, 1984
4420344 CMOS Source/drain implant process without compensation of polysilicon doping Dec. 13, 1983
4063274 Integrated circuit device including both N-channel and P-channel insulated gate field effect transistors Dec. 13, 1977
4032372 Epitaxial outdiffusion technique for integrated bipolar and field effect transistors Jun. 28, 1977

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