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Class Information
Number: 257/211
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Gate arrays > With particular signal path connections > Multi-level metallization
Description: Subject matter wherein the particular signal path connections include more than one layer of conductive metal deposited on a substrate.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7626266 |
Semiconductor integrated circuit device having a plurality of functional circuits with low power consumption |
Dec. 1, 2009 |
| 7622757 |
Semiconductor device having multiple wiring layers |
Nov. 24, 2009 |
| 7605409 |
Semiconductor device, method of manufacturing the same, sense amplifier and method of forming the same |
Oct. 20, 2009 |
| 7601994 |
Display device and method for manufacturing the same |
Oct. 13, 2009 |
| 7592710 |
Bond pad structure for wire bonding |
Sep. 22, 2009 |
| 7586132 |
Power FET with low on-resistance using merged metal layers |
Sep. 8, 2009 |
| 7576440 |
Semiconductor chip having bond pads and multi-chip package |
Aug. 18, 2009 |
| 7573135 |
Electronic parts packaging structure in which a semiconductor chip is mounted on a wiring substrate and buried in an insulation film |
Aug. 11, 2009 |
| 7566945 |
Semiconductor devices including nanotubes |
Jul. 28, 2009 |
| 7557449 |
Flexible via design to improve reliability |
Jul. 7, 2009 |
| 7550790 |
D/A conversion circuit and semiconductor device |
Jun. 23, 2009 |
| 7550788 |
Semiconductor device having fuse element arranged between electrodes formed in different wiring layers |
Jun. 23, 2009 |
| 7547973 |
Tamper-resistant semiconductor device |
Jun. 16, 2009 |
| 7547977 |
Semiconductor chip having bond pads |
Jun. 16, 2009 |
| 7544977 |
Mixed-scale electronic interface |
Jun. 9, 2009 |
| 7540970 |
Methods of fabricating a semiconductor device |
Jun. 2, 2009 |
| 7541625 |
Semiconductor integrated circuit |
Jun. 2, 2009 |
| 7535036 |
Semiconductor device and method of manufacturing the same |
May. 19, 2009 |
| 7535035 |
Cross-point nonvolatile memory devices using binary metal oxide layer as data storage material layer and methods of fabricating the same |
May. 19, 2009 |
| 7525198 |
Wiring structure of a semiconductor device |
Apr. 28, 2009 |
| 7525132 |
Semiconductor integrated circuit wiring design method and semiconductor integrated circuit |
Apr. 28, 2009 |
| 7514793 |
Metal interconnection lines of semiconductor devices and methods of forming the same |
Apr. 7, 2009 |
| 7508238 |
Semiconductor integrated circuit device |
Mar. 24, 2009 |
| 7501668 |
Semiconductor memory devices having contact pads with silicide caps thereon |
Mar. 10, 2009 |
| 7501710 |
Semiconductor integrated circuit and method of manufacturing the same |
Mar. 10, 2009 |
| 7495294 |
Flash devices with shared word lines |
Feb. 24, 2009 |
| 7489537 |
Nano-electronic memory array |
Feb. 10, 2009 |
| 7489018 |
Transistor |
Feb. 10, 2009 |
| 7482644 |
Integrated semiconductor memory and method for electrically stressing an integrated semiconductor memory |
Jan. 27, 2009 |
| 7482750 |
Plasma extraction microcavity plasma device and method |
Jan. 27, 2009 |
| 7479671 |
Thin film phase change memory cell formed on silicon-on-insulator substrate |
Jan. 20, 2009 |
| 7476945 |
Memory having reduced memory cell size |
Jan. 13, 2009 |
| 7476971 |
Via line barrier and etch stop structure |
Jan. 13, 2009 |
| 7465975 |
Top layers of metal for high performance IC's |
Dec. 16, 2008 |
| 7466028 |
Semiconductor contact structure |
Dec. 16, 2008 |
| 7462895 |
Signal line for display device and thin film transistor array panel including the signal line |
Dec. 9, 2008 |
| 7462900 |
Phase changeable memory devices including nitrogen and/or silicon |
Dec. 9, 2008 |
| 7453159 |
Semiconductor chip having bond pads |
Nov. 18, 2008 |
| 7446352 |
Dynamic array architecture |
Nov. 4, 2008 |
| 7446418 |
Semiconductor device for preventing defective filling of interconnection and cracking of insulating film |
Nov. 4, 2008 |
| 7442626 |
Rectangular contact used as a low voltage fuse element |
Oct. 28, 2008 |
| 7442969 |
Top layers of metal for high performance IC's |
Oct. 28, 2008 |
| 7436008 |
Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device |
Oct. 14, 2008 |
| 7425764 |
Top layers of metal for high performance IC's |
Sep. 16, 2008 |
| 7425735 |
Multi-layer phase-changeable memory devices |
Sep. 16, 2008 |
| 7423300 |
Single-mask phase change memory element |
Sep. 9, 2008 |
| 7423285 |
Wire cross-point fet structure |
Sep. 9, 2008 |
| 7418692 |
Method for designing structured ASICS in silicon processes with three unique masking steps |
Aug. 26, 2008 |
| 7417301 |
Semiconductor component with coreless transformer |
Aug. 26, 2008 |
| 7414275 |
Multi-level interconnections for an integrated circuit chip |
Aug. 19, 2008 |
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