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Class Information
Number: 257/210
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Gate arrays > With particular signal path connections > With wiring channel area
Description: Subject matter wherein the signal paths in the array are located in an area separate from the active devices forming the elements of the array.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7592710 |
Bond pad structure for wire bonding |
Sep. 22, 2009 |
| 7554207 |
Method of forming a lamination film pattern and improved lamination film pattern |
Jun. 30, 2009 |
| 7550790 |
D/A conversion circuit and semiconductor device |
Jun. 23, 2009 |
| 7528455 |
Narrow width metal oxide semiconductor transistor |
May. 5, 2009 |
| 7514728 |
Semiconductor integrated circuit device using four-terminal transistors |
Apr. 7, 2009 |
| 7511318 |
Electromechanical memory array using nanotube ribbons and method for making same |
Mar. 31, 2009 |
| 7488996 |
Thin film transistor array panel for a liquid crystal display |
Feb. 10, 2009 |
| 7476915 |
Semiconductor integrated circuit including a first region and a second region |
Jan. 13, 2009 |
| 7468551 |
Multiple chips bonded to packaging structure with low noise and multiple selectable functions |
Dec. 23, 2008 |
| 7456447 |
Semiconductor integrated circuit device |
Nov. 25, 2008 |
| 7446418 |
Semiconductor device for preventing defective filling of interconnection and cracking of insulating film |
Nov. 4, 2008 |
| 7402846 |
Electrostatic discharge (ESD) protection structure and a circuit using the same |
Jul. 22, 2008 |
| 7388260 |
Structure for spanning gap in body-bias voltage routing structure |
Jun. 17, 2008 |
| 7374986 |
Method of fabricating field effect transistor (FET) having wire channels |
May. 20, 2008 |
| 7368767 |
Semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells and design method of fixing its well potential |
May. 6, 2008 |
| 7365376 |
Semiconductor integrated circuit |
Apr. 29, 2008 |
| 7365377 |
Semiconductor integrated circuit device using four-terminal transistors |
Apr. 29, 2008 |
| 7358549 |
Multi-layered metal routing technique |
Apr. 15, 2008 |
| 7352048 |
Integration of barrier layer and seed layer |
Apr. 1, 2008 |
| 7345352 |
Insulating tube, semiconductor device employing the tube, and method of manufacturing the same |
Mar. 18, 2008 |
| 7332817 |
Die and die-package interface metallization and bump design and arrangement |
Feb. 19, 2008 |
| 7332753 |
Semiconductor device, wafer and method of designing and manufacturing the same |
Feb. 19, 2008 |
| 7321139 |
Transistor layout for standard cell with optimized mechanical stress effect |
Jan. 22, 2008 |
| 7274051 |
Field effect transistor (FET) having wire channels and method of fabricating the same |
Sep. 25, 2007 |
| 7265396 |
Semiconductor device |
Sep. 4, 2007 |
| 7259441 |
Hollow structure in an integrated circuit and method for producing such a hollow structure in an integrated circuit |
Aug. 21, 2007 |
| 7230286 |
Vertical FET with nanowire channels and a silicided bottom contact |
Jun. 12, 2007 |
| 7227254 |
Integrated circuit package |
Jun. 5, 2007 |
| 7227202 |
Semiconductor device and cell |
Jun. 5, 2007 |
| 7217966 |
Self-protecting transistor array |
May. 15, 2007 |
| 7206552 |
Semiconductor switching device |
Apr. 17, 2007 |
| 7196363 |
Multilayer metal structure of supply rings with large parasitic capacitance |
Mar. 27, 2007 |
| 7183594 |
Configurable gate array cell with extended poly gate terminal |
Feb. 27, 2007 |
| 7132752 |
Semiconductor chip and semiconductor device including lamination of semiconductor chips |
Nov. 7, 2006 |
| 7132751 |
Memory cell using silicon carbide |
Nov. 7, 2006 |
| 7119383 |
Arrangement of wiring lines including power source lines and channel wirings of a semiconductor integrated circuit having plural cells |
Oct. 10, 2006 |
| 7098512 |
Layout patterns for deep well region to facilitate routing body-bias voltage |
Aug. 29, 2006 |
| 7084440 |
Integrated circuit layout and a semiconductor device manufactured using the same |
Aug. 1, 2006 |
| 7068068 |
Re-configurable mixed-mode integrated circuit architecture |
Jun. 27, 2006 |
| 7064440 |
Semiconductor device |
Jun. 20, 2006 |
| 7053424 |
Semiconductor integrated circuit device and its manufacture using automatic layout |
May. 30, 2006 |
| 7023070 |
Semiconductor device |
Apr. 4, 2006 |
| 6974979 |
Nonvolatile semiconductor memory |
Dec. 13, 2005 |
| 6972444 |
Wafer with saw street guide |
Dec. 6, 2005 |
| 6967406 |
Semiconductor integrated circuit |
Nov. 22, 2005 |
| 6940108 |
Slot design for metal interconnects |
Sep. 6, 2005 |
| 6936898 |
Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions |
Aug. 30, 2005 |
| 6919591 |
Thin film transistor array panel for a liquid crystal display |
Jul. 19, 2005 |
| 6914326 |
Solder ball landpad design to improve laminate performance |
Jul. 5, 2005 |
| 6909189 |
Semiconductor device with dummy structure |
Jun. 21, 2005 |
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