| Class Number |
Class Name |
No. of Patents |
| 257/797 |
Alignment marks |
723 |
| 257/E25.001 |
Assemblies consisting of plurality of individual semiconductor or other solid-state devices (epo) |
6 |
| 257/E25.002 |
All devices being of same type, e.g., assemblies of rectifier diodes (epo) |
7 |
| 257/E25.022 |
Devices having separate containers (epo) |
50 |
| 257/E25.023 |
Device consisting of plurality of semiconductor or other solid-state devices or components formed in or on common substrate, e.g., integrated circuit device (epo) |
802 |
| 257/E25.028 |
Incoherent light-emitting semiconductor devices having potential or surface barrier (epo) |
95 |
| 257/E25.024 |
Semiconductors devices adapted for rectifying, amplifying, oscillating, or switching, capacitors, or resistors with at least one potential-jump barrier or surface barrier (epo) |
6 |
| 257/E25.026 |
Devices being arranged next to each other (epo) |
107 |
| 257/E25.025 |
Mixed assemblies (epo) |
74 |
| 257/E25.027 |
Stacked arrangements of devices (epo) |
103 |
| 257/E25.003 |
Devices not having separate containers (epo) |
8 |
| 257/E25.01 |
Device consisting of plurality of semiconductor or other solid state devices or components formed in or on common substrate, e.g., integrated circuit device (epo) |
69 |
| 257/E25.011 |
Devices being arranged next and on each other, i.e., mixed assemblies (epo) |
466 |
| 257/E25.012 |
Devices being arranged next to each other (epo) |
470 |
| 257/E25.013 |
Stacked arrangements of devices (epo) |
1332 |
| 257/E25.004 |
Devices responsive or sensitive to electromagnetic radiation, e.g., infrared radiation, adapted for conversion of radiation into electrical energy or for control of electrical energy by such radiation (epo) |
5 |
| 257/E25.005 |
Devices being arranged next to each other (epo) |
54 |
| 257/E25.006 |
Stacked arrangements of devices (epo) |
108 |
| 257/E25.007 |
Devices being solar cells (epo) |
57 |
| 257/E25.019 |
Incoherent light-emitting semiconductor devices having potential or surface barrier (epo) |
13 |
| 257/E25.02 |
Devices being arranged next to each other (epo) |
326 |
| 257/E25.021 |
Stacked arrangements of devices (epo) |
91 |
| 257/E25.008 |
Organic solid-state devices (epo) |
28 |
| 257/E25.009 |
Devices responsive or sensitive to electromagnetic radiation, e.g., infrared radiation, adapted for conversion of radiation into electrical energy or for control of electrical energy by such radiation, e.g., photovoltaic modules based on organic solar cells (epo) |
5 |
| 257/E25.014 |
Semiconductor devices adapted for rectifying, amplifying, oscillating, or switching, capacitors, or resistors with at least one potential-jump barrier or surface barrier (epo) |
13 |
| 257/E25.017 |
Apertured devices mounted on one or more rods passed through apertures (epo) |
6 |
| 257/E25.015 |
Devices being arranged next and on each other, i.e., mixed assemblies (epo) |
36 |
| 257/E25.016 |
Devices being arranged next to each other (epo) |
330 |
| 257/E25.018 |
Stacked arrangements of nonapertured devices (epo) |
81 |
| 257/E25.029 |
Devices being of two or more types, e.g., forming hybrid circuits (epo) |
320 |
| 257/E25.032 |
Comprising optoelectronic devices, e.g., led, photodiodes (epo) |
310 |
| 257/E25.031 |
Containers (epo) |
147 |
| 257/E25.03 |
Devices being mounted on two or more different substrates (epo) |
135 |
| 257/603 |
Avalanche diode (e.g., so-called "zener" diode having breakdown voltage greater than 6 volts) |
214 |
| 257/604 |
Microwave transit time device (e.g., impatt diode) |
69 |
| 257/605 |
With means to limit area of breakdown (e.g., guard ring having higher breakdown voltage) |
85 |
| 257/606 |
Subsurface breakdown |
67 |
| 257/565 |
Bipolar transistor structure |
471 |
| 257/589 |
Avalanche transistor |
21 |
| 257/577 |
Including additional component in same, non-isolated structure (e.g., transistor with diode, transistor with resistor, etc.) |
353 |
| 257/566 |
Plural non-isolated transistor structures in same structure |
126 |
| 257/574 |
Complementary transistors share common active region (e.g., integrated injection logic, i 2 l) |
87 |
| 257/575 |
Including lateral bipolar transistor structure |
175 |
| 257/576 |
With contacts of refractory material (e.g., polysilicon, silicide of refractory or platinum group metal) |
72 |
| 257/567 |
Darlington configuration (i.e., emitter to collector current of input transistor supplied to base region of output transistor) |
52 |
| 257/569 |
Complementary darlington-connected transistors |
19 |
| 257/568 |
More than two darlington-connected transistors |
25 |
| 257/571 |
Non-planar structure (e.g., mesa emitter, or having a groove to define resistor) |
60 |
| 257/570 |
With active components in addition to darlington transistors (e.g., antisaturation diode, bleeder diode connected antiparallel to input transistor base-emitter junction, etc.) |
44 |
| 257/573 |
With housing or contact structure or configuration |
26 |
| 257/572 |
With resistance means connected between transistor base regions |
39 |
| 257/592 |
With base region having specified doping concentration profile or specified configuration (e.g., inactive base more heavily doped than active base or base region has constant doping concentration portion (e.g., epitaxial base)) |
463 |
| 257/591 |
With emitter region having specified doping concentration profile (e.g., high-low concentration step) |
119 |
| 257/578 |
With enlarged emitter area (e.g., power device) |
138 |
| 257/582 |
With current ballasting means (e.g., emitter ballasting resistors or base current ballasting resistors) |
60 |
| 257/584 |
With housing or contact (i.e., electrode) means |
121 |
| 257/583 |
With means to reduce transistor action in selected portions of transistor (e.g., heavy base region doping under central web of emitter to prevent secondary breakdown) |
67 |
| 257/579 |
With separate emitter areas connected in parallel |
111 |
| 257/580 |
With current ballasting means (e.g., emitter ballasting resistors or base current ballasting means) |
63 |
| 257/581 |
Thin film ballasting means (e.g., polysilicon resistor) |
35 |
| 257/593 |
With means to increase current gain or operating frequency |
228 |
| 257/585 |
With means to increase inverse gain |
41 |
| 257/590 |
With means to reduce minority carrier lifetime (e.g., region of deep level dopant or region of crystal damage) |
75 |
| 257/586 |
With non-planar semiconductor surface (e.g., groove, mesa, bevel, etc.) |
338 |
| 257/587 |
With specified electrode means |
289 |
| 257/588 |
Including polycrystalline semiconductor as connection |
331 |
| 257/925 |
Bridge rectifier module |
24 |
| 257/1 |
Bulk effect device |
90 |
| 257/2 |
Bulk effect switching in amorphous material |
320 |
| 257/5 |
In array |
201 |
| 257/3 |
With means to localize region of conduction (e.g., "pore" structure) |
315 |
| 257/4 |
With specified electrode composition or configuration |
337 |
| 257/6 |
Intervalley transfer (e.g., gunn effect) |
52 |
| 257/7 |
In monolithic integrated circuit |
24 |
| 257/8 |
Three or more terminal device |
34 |
| 257/E47.001 |
Bulk negative resistance effect devices, e.g., gunn-effect devices, processes, or apparatus peculiar to manufacture or treatment of such devices, or of parts thereof (epo) |
15 |
| 257/E47.002 |
Gunn-effect devices or transferred electron devices (epo) |
17 |
| 257/E47.003 |
Controlled by electromagnetic radiation (epo) |
2 |
| 257/E47.004 |
Gunn diodes (epo) |
26 |
| 257/E47.005 |
Processes or apparatus peculiar to manufacture or treatment of these devices or of parts thereof (epo) |
4 |
| 257/912 |
Charge transfer device using both electron and hole signal carriers |
24 |
| 257/734 |
Combined with electrical contact or lead |
856 |
| 257/780 |
Ball or nail head type contact, lead, or bond |
1370 |
| 257/781 |
Layered contact, lead or bond |
656 |
| 257/735 |
Beam leads (i.e., leads that extend beyond the ends or sides of a chip component) |
374 |
| 257/736 |
Layered |
193 |
| 257/737 |
Bump leads |
1919 |
| 257/738 |
Ball shaped |
1739 |
| 257/785 |
By pressure alone |
221 |
| 257/777 |
Chip mounted on chip |
1873 |
| 257/786 |
Configuration or pattern of bonds |
1626 |
| 257/782 |
Die bond |
581 |
| 257/783 |
With adhesive means |
977 |
| 257/778 |
Flip chip |
2594 |
| 257/773 |
Of specified configuration |
1977 |
| 257/776 |
Cross-over arrangement, component or structure |
674 |
| 257/775 |
Varying width or thickness of conductor |
731 |
| 257/774 |
Via (interconnection hole) shape |
2280 |
| 257/741 |
Of specified material other than unalloyed aluminum |
296 |
| 257/771 |
Alloy containing aluminum |
239 |
| 257/749 |
At least portion of which is transparent to ultraviolet, visible or infrared light |
132 |
| 257/746 |
Composite material (e.g., fibers or strands embedded in solid matrix) |
149 |
| 257/744 |
For compound semiconductor material |
147 |
| 257/745 |
Contact for iii-v material |
203 |
| 257/750 |
Layered |
1018 |
| 257/766 |
At least one layer containing chromium or nickel |
358 |
| 257/762 |
At least one layer containing silver or copper |
886 |
| 257/761 |
At least one layer containing vanadium, hafnium, niobium, zirconium, or tantalum |
284 |
| 257/751 |
At least one layer forms a diffusion barrier |
1227 |
| 257/765 |
At least one layer of an alloy containing aluminum |
420 |
| 257/763 |
At least one layer of molybdenum, titanium, or tungsten |
850 |
| 257/764 |
Alloy containing molybdenum, titanium, or tungsten |
544 |
| 257/754 |
At least one layer of silicide or polycrystalline silicon |
522 |
| 257/756 |
Multiple polysilicon layers |
191 |
| 257/755 |
Polysilicon laminated with silicide |
312 |
| 257/757 |
Silicide of refractory or platinum group metal |
298 |
| 257/758 |
Multiple metal levels on semiconductor, separated by insulating layer (e.g., multiple level metallization for integrated circuit) |
2856 |
| 257/759 |
Including organic insulating material between metal levels |
633 |
| 257/760 |
Separating insulating layer is laminate or composite of plural insulating materials (e.g., silicon oxide on silicon nitride, silicon oxynitride) |
858 |
| 257/752 |
Planarized to top of insulating layer |
483 |
| 257/753 |
With adhesion promoting means (e.g., layer of material) to promote adhesion of contact to an insulating layer |
375 |
| 257/768 |
Refractory or platinum group metal or alloy or silicide thereof |
358 |
| 257/770 |
Molybdenum, tungsten, or titanium or their silicides |
315 |
| 257/769 |
Platinum group metal or silicide thereof |
182 |
| 257/767 |
Resistive to electromigration or diffusion of the contact or lead material |
404 |
| 257/772 |
Solder composition |
326 |
| 257/742 |
With a semiconductor conductivity substitution type dopant (e.g., germanium in the case of a gallium arsenide semiconductor) in a contact metal) |
70 |
| 257/743 |
For compound semiconductor material |
75 |
| 257/747 |
With thermal expansion matching of contact or lead material to semiconductor active device |
144 |
| 257/748 |
Plural layers of specified contact or lead material |
185 |
| 257/779 |
Solder wettable contact, lead, or bond |
881 |
| 257/784 |
Wire contact, lead, or bond |
1705 |
| 257/740 |
With means to prevent contact from penetrating shallow pn junction (e.g., prevention of aluminum "spiking") |
70 |
| 257/739 |
With textured surface |
129 |
| 257/212 |
Conductivity modulation device (e.g., unijunction transistor, double-base diode, conductivity-modulated transistor) |
97 |
| 257/920 |
Conductor layers on different levels connected in parallel (e.g., to reduce resistance) |
50 |
| 257/665 |
Contacts or leads including fusible link means or noise suppression means |
291 |
| 257/E27.001 |
Device consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate, e.g., integrated circuit device (epo) |
47 |
| 257/E27.122 |
Including active semiconductor component sensitive to infrared radiation, light, or electromagnetic radiation of a shorter wavelength (epo) |
29 |
| 257/E27.127 |
Device controlled by radiation (epo) |
40 |
| 257/E27.13 |
Imager including structural or functional details of the device (epo) |
133 |
| 257/E27.149 |
Bipolar transistor imager (epo) |
108 |
| 257/E27.15 |
Charge coupled imager (epo) |
136 |
| 257/E27.162 |
Anti-blooming (epo) |
224 |
| 257/E27.154 |
Area ccd imager (epo) |
500 |
| 257/E27.157 |
Frame transfer (epo) |
43 |
| 257/E27.155 |
Frame-interline transfer (epo) |
6 |
| 257/E27.156 |
Interline transfer (epo) |
71 |
| 257/E27.159 |
Ccd or cid color imager (epo) |
90 |
| 257/E27.158 |
Charge injection device (cid) imager (epo) |
35 |
| 257/E27.163 |
Including a photoconductive layer deposited on the ccd structure (epo) |
12 |
| 257/E27.16 |
Infrared ccd or cid imager (epo) |
95 |
| 257/E27.161 |
Of the hybrid type (e.g., chip-on-chip, bonded substrates) (epo) |
116 |
| 257/E27.153 |
Linear ccd imager (epo) |
94 |
| 257/E27.151 |
Structural or functional details (epo) |
162 |
| 257/E27.152 |
Geometry or disposition of pixel-elements, address lines or gate-electrodes (epo) |
145 |
| 257/E27.147 |
Contact-type imager (e.g., contacts document surface) (epo) |
36 |
| 257/E27.131 |
Geometry or disposition of pixel-elements, address-lines, or gate-electrodes (epo) |
247 |
| 257/E27.141 |
Imager using a photoconductor layer (e.g., single photoconductor layer for all pixels) (epo) |
261 |
| 257/E27.145 |
Anti-blooming (epo) |
19 |
| 257/E27.142 |
Color imager (epo) |
26 |
| 257/E27.143 |
Infrared imager (epo) |
51 |
| 257/E27.144 |
Of the hybrid type (e.g., chip-on-chip, bonded substrates) (epo) |
41 |
| 257/E27.146 |
X-ray, gamma-ray, or high energy radiation imagers (epo) |
87 |
| 257/E27.148 |
Junction field effect transistor (jfet) imager or static induction transistor (sit) imager (epo) |
79 |
| 257/E27.133 |
Photodiode array or mos imager (epo) |
772 |
| 257/E27.139 |
Anti-blooming (epo) |
63 |
| 257/E27.134 |
Color imager (epo) |
137 |
| 257/E27.135 |
Multicolor imager having a stacked pixel-element structure, e.g. npn, npnpn or mqw elements (epo) |
41 |
| 257/E27.136 |
Infrared imager (epo) |
131 |
| 257/E27.138 |
Multispectral infrared imager having a stacked pixel-element structure, e.g., npn, npnpn or mqw structures (epo) |
24 |
| 257/E27.137 |
Of the hybrid type (e.g., chip-on-chip, bonded substrates) (epo) |
132 |
| 257/E27.14 |
X-ray, gamma-ray, or high energy radiation imager (measuring x-, gamma- or corpuscular radiation) (epo) |
78 |
| 257/E27.132 |
Pixel-elements with integrated switching, control, storage, or amplification elements (epo) |
535 |
| 257/E27.128 |
With at least one potential barrier or surface barrier (epo) |
293 |
| 257/E27.129 |
In a repetitive configuration (epo) |
165 |
| 257/E27.123 |
Energy conversion device (epo) |
60 |
| 257/E27.124 |
In a repetitive configuration, e.g. planar multi-junction solar cells (epo) |
60 |
| 257/E27.126 |
Including multiple vertical junction or v-groove junction solar cells formed in a semiconductor substrate (epo) |
29 |
| 257/E27.125 |
Including only thin film solar cells deposited on a substrate (epo) |
235 |
| 257/E27.002 |
Including bulk negative resistance effect component (epo) |
8 |
| 257/E27.003 |
Including gunn-effect device (epo) |
3 |
| 257/E27.005 |
Including component using galvano-magnetic effects, e.g. hall effect (epo) |
383 |
| 257/E27.114 |
Including only passive thin-film or thick-film elements on a common insulating substrate (epo) |
43 |
| 257/E27.115 |
Thick-film circuits (epo) |
43 |
| 257/E27.116 |
Thin-film circuits (epo) |
97 |
| 257/E27.117 |
Including organic material in active region |
23 |
| 257/E27.118 |
Including semiconductor components sensitive to infrared radiation, light, or electromagnetic radiation of a shorter wavelength (epo) |
2 |
| 257/E27.119 |
Including semiconductor components with at least one potential barrier, surface barrier, or recombination zone adapted for light emission (epo) |
32 |
| 257/E27.006 |
Including piezo-electric, electro-resistive, or magneto-resistive component (epo) |
144 |
| 257/E27.12 |
Including semiconductor component with at least one potential barrier or surface barrier adapted for light emission structurally associated with controlling devices having a variable impedance and not being light sensitive (epo) |
212 |
| 257/E27.121 |
In a repetitive configuration (epo) |
188 |
| 257/E27.009 |
Including semiconductor component with at least one potential barrier or surface barrier adapted for rectifying, oscillating, amplifying, or switching, or including integrated passive circuit elements (epo) |
76 |
| 257/E27.111 |
Substrate comprising other than a semiconductor material, e.g. insulating substrate or layered substrate including a non-semiconductor layer (epo) |
1825 |
| 257/E27.113 |
Combined with thin-film or thick-film passive component (epo) |
45 |
| 257/E27.112 |
Including insulator on semiconductor, e.g. soi (silicon on insulator) (epo) |
1550 |
| 257/E27.01 |
With semiconductor substrate only (epo) |
33 |
| 257/E27.011 |
Including a plurality of components in a non-repetitive configuration (epo) |
28 |
| 257/E27.028 |
Including component having an active region in common (epo) |
7 |
| 257/E27.029 |
Including component of the field-effect type (epo) |
56 |
| 257/E27.03 |
In combination with bipolar transistor and diode, capacitor, or resistor (epo) |
17 |
| 257/E27.032 |
In combination with lateral bipolar transistor and diode, capacitor, or resistor (epo) |
45 |
| 257/E27.031 |
In combination with vertical bipolar transistor and diode, capacitor, or resistor (epo) |
123 |
| 257/E27.033 |
In combination with diode, capacitor, or resistor (epo) |
107 |
| 257/E27.034 |
In combination with capacitor only (epo) |
37 |
| 257/E27.035 |
In combination with resistor only (epo) |
30 |
| 257/E27.036 |
With component other than field-effect type (epo) |
12 |
| 257/E27.037 |
Bipolar transistor in combination with diode, capacitor, or resistor (epo) |
18 |
| 257/E27.043 |
Lateral bipolar transistor in combination with diode, capacitor, or resistor (epo) |
6 |
| 257/E27.038 |
Vertical bipolar transistor in combination with diode, capacitor, or resistor (epo) |
38 |
| 257/E27.042 |
Vertical bipolar transistor in combination with capacitor only (epo) |
13 |
| 257/E27.039 |
Vertical bipolar transistor in combination with diode only (epo) |
42 |
| 257/E27.04 |
With schottky diode only (epo) |
49 |
| 257/E27.041 |
Vertical bipolar transistor in combination with resistor only (epo) |
44 |
| 257/E27.044 |
Including combination of diode, capacitor, or resistor (epo) |
14 |
| 257/E27.045 |
Combination of capacitor and resistor (epo) |
15 |
| 257/E27.026 |
Integrated circuit having a three-dimensional layout (epo) |
666 |
| 257/E27.027 |
Including components formed on opposite sides of a semiconductor substrate (epo) |
0 |
| 257/E27.013 |
Integrated circuit having a two-dimensional layout of components without a common active region (epo) |
24 |
| 257/E27.014 |
Including a field-effect type component (epo) |
59 |
| 257/E27.015 |
In combination with bipolar transistor (epo) |
587 |
| 257/E27.017 |
In combination with bipolar transistor and diode, resistor, or capacitor (epo) |
111 |
| 257/E27.016 |
In combination with diode, resistor, or capacitor (epo) |
551 |
| 257/E27.018 |
With component other than field-effect type (epo) |
18 |
| 257/E27.019 |
Bipolar transistor in combination with diode, capacitor, or resistor (epo) |
26 |
| 257/E27.023 |
Lateral bipolar transistor in combination with diode, capacitor, or resistor (epo) |
11 |
| 257/E27.02 |
Vertical bipolar transistor in combination with diode, capacitor, or resistor (epo) |
36 |
| 257/E27.022 |
Vertical bipolar transistor in combination with diode only (epo) |
37 |
| 257/E27.021 |
Vertical bipolar transistor in combination with resistor or capacitor only (epo) |
52 |
| 257/E27.024 |
Including combination of diode, capacitor, or resistor (epo) |
53 |
| 257/E27.025 |
Including combination of capacitor or resistor only (epo) |
25 |
| 257/E27.012 |
Made of compound semiconductor material, e.g. iii-v material (epo) |
398 |
| 257/E27.07 |
Including a plurality of individual components in a repetitive configuration (epo) |
69 |
| 257/E27.072 |
Including bipolar component (epo) |
1 |
| 257/E27.074 |
Including bipolar transistor (epo) |
14 |
| 257/E27.076 |
Array of single bipolar transistors only, e.g. read only memory structure (epo) |
15 |
| 257/E27.075 |
Bipolar dynamic random access memory structure (epo) |
27 |
| 257/E27.078 |
Bipolar electrically programmable memory structure (epo) |
55 |
| 257/E27.077 |
Static bipolar memory cell structure (epo) |
84 |
| 257/E27.073 |
Including diode only (epo) |
122 |
| 257/E27.079 |
Thyristor (epo) |
18 |
| 257/E27.08 |
Unijunction transistor, i.e., three terminal device with only one p-n junction having a negative resistance region in the i-v characteristic (epo) |
3 |
| 257/E27.081 |
Including field-effect component (epo) |
1272 |
| 257/E27.084 |
Dynamic random access memory, dram, structure (epo) |
515 |
| 257/E27.085 |
One-transistor memory cell structure, i.e., each memory cell containing only one transistor (epo) |
539 |
| 257/E27.095 |
Capacitor and transistor in common trench (epo) |
18 |
| 257/E27.096 |
Vertical transistor (epo) |
252 |
| 257/E27.09 |
Capacitor extending under the transistor (epo) |
69 |
| 257/E27.092 |
Capacitor in trench (epo) |
383 |
| 257/E27.093 |
Capacitor extending under or around the transistor (epo) |
103 |
| 257/E27.094 |
Having storage electrode extension stacked over the transistor (epo) |
78 |
| 257/E27.086 |
Storage electrode stacked over the transistor |
584 |
| 257/E27.089 |
Storage electrode having multiple wings (epo) |
677 |
| 257/E27.087 |
With bit line higher than capacitor (epo) |
200 |
| 257/E27.088 |
With capacitor higher than bit line level (epo) |
391 |
| 257/E27.091 |
Transistor in trench (epo) |
187 |
| 257/E27.097 |
Peripheral structure (epo) |
390 |
| 257/E27.082 |
Including bucket brigade type charge coupled device (c.c.d) (epo) |
24 |
| 257/E27.083 |
Including charge coupled device (c.c.d) or charge injection device (c.i.d) (epo) |
122 |
| 257/E27.102 |
Read-only memory, rom, structure (epo) |
645 |
| 257/E27.103 |
Electrically programmable rom (epo) |
3071 |
| 257/E27.104 |
Ferroelectric non-volatile memory structure (epo) |
801 |
| 257/E27.098 |
Static random access memory, sram, structure (epo) |
409 |
| 257/E27.099 |
Load element being a mosfet transistor (epo) |
529 |
| 257/E27.1 |
Load element being a thin film transistor (epo) |
362 |
| 257/E27.101 |
Load element being a resistor (epo) |
420 |
| 257/E27.071 |
Including resistor or capacitor only (epo) |
113 |
| 257/E27.105 |
Masterslice integrated circuit (epo) |
236 |
| 257/E27.11 |
Input and output buffer/driver (epo) |
139 |
| 257/E27.106 |
Using bipolar structure (epo) |
52 |
| 257/E27.109 |
Using combined field-effect/bipolar structure (epo) |
37 |
| 257/E27.107 |
Using field-effect structure (epo) |
115 |
| 257/E27.108 |
Cmos gate array (epo) |
377 |
| 257/E27.046 |
Including only semiconductor components of a single kind, e.g., all bipolar transistors, all diodes, or all cmos (epo) |
378 |
| 257/E27.053 |
Bipolar component only (epo) |
58 |
| 257/E27.054 |
Combination of lateral and vertical transistors only (epo) |
101 |
| 257/E27.055 |
Vertical bipolar transistor only (epo) |
48 |
| 257/E27.058 |
Combination of direct and inverse vertical transistors (e.g., collector acts as emitter) (epo) |
17 |
| 257/E27.057 |
Vertical complementary transistor (epo) |
118 |
| 257/E27.056 |
Vertical direct transistor of the same conductivity type having different characteristics, (e.g. darlington transistor) (epo) |
95 |
| 257/E27.048 |
Capacitor only (epo) |
417 |
| 257/E27.05 |
Metal-insulated-semiconductor (mis) diode (epo) |
34 |
| 257/E27.049 |
Varactor diode (epo) |
51 |
| 257/E27.051 |
Diode only (epo) |
145 |
| 257/E27.059 |
Including field-effect component only (epo) |
49 |
| 257/E27.06 |
Field-effect transistor with insulated gate (epo) |
634 |
| 257/E27.061 |
Combination of depletion and enhancement field-effect transistors (epo) |
84 |
| 257/E27.062 |
Complementary mis (epo) |
538 |
| 257/E27.064 |
Combination of complementary transistors having a different structure, e.g. stacked cmos, high-voltage and low-voltage cmos (epo) |
404 |
| 257/E27.066 |
Including a p-well only in the substrate (epo) |
68 |
| 257/E27.065 |
Including an n-well only in the substrate (epo) |
57 |
| 257/E27.067 |
Including both n- and p- wells in the substrate, e.g. twin-tub (epo) |
378 |
| 257/E27.063 |
Means for preventing a parasitic bipolar action between the different transistor regions, e.g. latch-up prevention (epo) |
272 |
| 257/E27.069 |
Pn junction gate field-effect transistor |
46 |
| 257/E27.068 |
Schottky barrier gate field-effect transistor (epo) |
85 |
| 257/E27.047 |
Resistor only (epo) |
273 |
| 257/E27.052 |
Thyristor only (epo) |
59 |
| 257/E27.004 |
Including solid state component for rectifying, amplifying, or switching without a potential barrier or surface barrier (epo) |
271 |
| 257/E27.007 |
Including superconducting component (epo) |
58 |
| 257/E27.008 |
Including thermo-electric or thermo-magnetic component with or without a junction of dissimilar material or thermo-magnetic component (epo) |
74 |
| 257/E39.001 |
Devices using superconductivity, processes, or apparatus peculiar to manufacture or treatment of such devices, or of parts thereof (epo) |
10 |
| 257/E39.004 |
Characterized by current path (epo) |
2 |
| 257/E39.006 |
Characterized by material (epo) |
64 |
| 257/E39.009 |
Ceramic materials (epo) |
21 |
| 257/E39.01 |
Comprising copper oxide (epo) |
271 |
| 257/E39.011 |
Multilayered structures, e.g., super lattices (epo) |
34 |
| 257/E39.007 |
Organic materials (epo) |
44 |
| 257/E39.008 |
Fullerene superconductors, e.g., soccerball-shaped allotrope of carbon, e.g., c60, c94 (epo) |
9 |
| 257/E39.005 |
Characterized by shape of element (epo) |
3 |
| 257/E39.002 |
Containers or mountings (epo) |
12 |
| 257/E39.003 |
For josephson devices (epo) |
5 |
| 257/E39.012 |
Devices comprising junction of dissimilar materials, e.g., josephson-effect devices (epo) |
16 |
| 257/E39.014 |
Josephson-effect devices (epo) |
89 |
| 257/E39.015 |
Comprising high tc ceramic materials (epo) |
140 |
| 257/E39.013 |
Single electron tunnelling devices (epo) |
5 |
| 257/E39.016 |
Three or more electrode devices, e.g., transistor-like structures (epo) |
69 |
| 257/E39.017 |
Permanent superconductor devices (epo) |
122 |
| 257/E39.018 |
Comprising high tc ceramic materials (epo) |
229 |
| 257/E39.019 |
Three or more electrode devices (epo) |
11 |
| 257/E39.02 |
Field-effect devices (epo) |
66 |
| 257/927 |
Different doping levels in different parts of pn junction to produce shaped depletion layer |
27 |
| 257/910 |
Diode arrays (e.g., diode read-only memory array) |
65 |
| 257/908 |
Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines |
112 |
| 257/906 |
Dram with capacitor electrodes used for accessing (e.g., bit line is capacitor plate) |
159 |
| 257/919 |
Elements of similar construction connected in series or parallel to average out manufacturing variations in characteristics |
27 |
| 257/926 |
Elongated lead extending axially through another elongated lead |
90 |
| 257/787 |
Encapsulated |
1874 |
| 257/796 |
With heat sink embedded in encapsulant |
504 |
| 257/788 |
With specified encapsulant |
442 |
| 257/793 |
Including epoxide |
262 |
| 257/794 |
Including glass |
126 |
| 257/792 |
Including polyimide |
182 |
| 257/791 |
Including polysiloxane (e.g., silicone resin) |
162 |
| 257/790 |
Plural encapsulating layers |
328 |
| 257/789 |
With specified filler material |
305 |
| 257/795 |
With specified filler material |
244 |
| 257/903 |
Fet configuration adapted for use as static memory cell |
630 |
| 257/904 |
With passive components, (e.g., polysilicon resistors) |
286 |
| 257/902 |
Fet with metal source region |
25 |
| 257/213 |
Field effect device |
333 |
| 257/214 |
Charge injection device |
86 |
| 257/215 |
Charge transfer device |
190 |
| 257/240 |
Changing width or direction of channel (e.g., meandering channel) |
131 |
| 257/243 |
Channel confinement |
122 |
| 257/244 |
Comprising a groove |
53 |
| 257/235 |
Electrical input |
68 |
| 257/238 |
Input signal responsive to signal charge in charge transfer device (e.g., regeneration or feedback) |
77 |
| 257/236 |
Signal applied to field effect electrode |
199 |
| 257/237 |
Charge-presetting/linear input type (e.g., fill and spill) |
75 |
| 257/216 |
Majority signal carrier (e.g., buried or bulk channel, or peristaltic) |
103 |
| 257/224 |
Channel confinement |
99 |
| 257/217 |
Having a conductive means in direct contact with channel (e.g., non-insulated gate) |
74 |
| 257/218 |
High resistivity channel (e.g., accumulation mode) or surface channel (e.g., transfer of signal charge occurs at the surface of the semiconductor) or minority carriers at input (i.e., surface channel input) |
45 |
| 257/219 |
Impurity concentration variation |
73 |
| 257/221 |
Along the length of the channel (e.g., doping variations for transfer directionality) |
117 |
| 257/220 |
Vertically within channel (e.g., profiled) |
63 |
| 257/222 |
Responsive to non-electrical external signal (e.g., imager) |
362 |
| 257/223 |
Having structure to improve output signal (e.g., antiblooming drain) |
286 |
| 257/241 |
Multiple channels (e.g., converging or diverging or parallel channels) |
242 |
| 257/225 |
Non-electrical input responsive (e.g., light responsive imager, input programmed by size of storage sites for use as a read-only memory, etc.) |
247 |
| 257/231 |
2-dimensional area architecture |
256 |
| 257/232 |
Having alternating strips of sensor structures and register structures (e.g., interline imager) |
327 |
| 257/233 |
Sensors not overlaid by electrode (e.g., photodiodes) |
503 |
| 257/229 |
Having structure to improve output signal (e.g., exposure control structure) |
253 |
| 257/230 |
With blooming suppression structure |
170 |
| 257/228 |
Light responsive, back illuminated |
88 |
| 257/226 |
Sensor element and charge transfer device are of different materials or on different substrates (e.g., "hybrid") |
120 |
| 257/234 |
Single strip of sensors (e.g., linear imager) |
149 |
| 257/227 |
With specified dopant (e.g., photoionizable, "extrinsic" detectors for infrared) |
56 |
| 257/239 |
Signal charge detection type (e.g., floating diffusion or floating gate non-destructive output) |
395 |
| 257/245 |
Structure for applying electric field into device (e.g., resistive electrode, acoustic traveling wave in channel) |
151 |
| 257/249 |
Electrode structures or materials |
245 |
| 257/250 |
Plural gate levels |
273 |
| 257/246 |
Phase structure (e.g., doping variations to provide asymmetry for 2-phase operation; more than four phases or "electrode per bit") |
117 |
| 257/248 |
2-phase |
131 |
| 257/247 |
Uniphase or virtual phase structure |
80 |
| 257/251 |
Substantially incomplete signal charge transfer (e.g., bucket brigade) |
43 |
| 257/242 |
Vertical charge transfer |
73 |
| 257/288 |
Having insulated electrode (e.g., mosfet, mos diode) |
935 |
| 257/412 |
Gate electrode of refractory material (e.g., polysilicon or a silicide of a refractory or platinum group metal) |
811 |
| 257/413 |
Polysilicon laminated with silicide |
412 |
| 257/410 |
Gate insulator includes material (including air or vacuum) other than sio 2 |
673 |
| 257/411 |
Composite or layered gate insulator (e.g., mixture such as silicon oxynitride) |
698 |
| 257/408 |
Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, ldd device) |
1044 |
| 257/296 |
Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell) |
2602 |
| 257/300 |
Capacitor coupled to, or forms gate of, insulated gate field effect transistor (e.g., non-destructive readout dynamic memory cell structure) |
695 |
| 257/298 |
Capacitor for signal storage in combination with non-volatile storage means |
495 |
| 257/301 |
Capacitor in trench |
1021 |
| 257/303 |
Stacked capacitor |
850 |
| 257/304 |
Storage node isolated by dielectric from semiconductor substrate |
460 |
| 257/302 |
Vertical transistor |
636 |
| 257/305 |
With means to insulate adjacent storage nodes (e.g., channel stops or field oxide) |
307 |
| 257/313 |
Inversion layer capacitor |
149 |
| 257/306 |
Stacked capacitor |
1717 |
| 257/307 |
Parallel interleaved capacitor electrode pairs (e.g., interdigitized) |
281 |
| 257/308 |
With capacitor electrodes connection portion located centrally thereof (e.g., fin electrodes with central post) |
387 |
| 257/309 |
With increased effective electrode surface area (e.g., tortuous path, corrugated, or textured electrodes) |
608 |
| 257/311 |
Storage node isolated by dielectric from semiconductor substrate |
375 |
| 257/299 |
Structure configured for voltage converter (e.g., charge pump, substrate bias generator) |
147 |
| 257/312 |
Voltage variable capacitor (i. e., capacitance varies with applied voltage) |
154 |
| 257/310 |
With high dielectric constant insulator (e.g., ta 2 o 5 ) |
937 |
| 257/297 |
With means for preventing charge leakage due to minority carrier generation (e.g., alpha generated soft error protection or "dark current" leakage protection) |
247 |
| 257/367 |
Insulated gate controlled breakdown of pn junction (e.g., field plate diode) |
96 |
| 257/368 |
Insulated gate field effect transistor in integrated circuit |
823 |
| 257/378 |
Combined with bipolar transistor |
534 |
| 257/379 |
Combined with passive components (e.g., resistors) |
609 |
| 257/380 |
Polysilicon resistor |
239 |
| 257/381 |
With multiple levels of polycrystalline silicon |
95 |
| 257/369 |
Complementary insulated gate field effect transistors |
1326 |
| 257/370 |
Combined with bipolar transistor |
579 |
| 257/371 |
Complementary transistors in wells of opposite conductivity types more heavily doped than the substrate region in which they are formed, e.g., twin wells |
624 |
| 257/372 |
With means to prevent latchup or parasitic conduction channels |
369 |
| 257/373 |
With pn junction to collect injected minority carriers to prevent parasitic bipolar transistor action |
145 |
| 257/374 |
Dielectric isolation means (e.g., dielectric layer in vertical grooves) |
440 |
| 257/376 |
With barrier region of reduced minority carrier lifetime (e.g., heavily doped p+ region to reduce electron minority carrier lifetime, or containing deep level impurity or crystal damage), or with region of high threshold voltage (e.g., heavily doped channel stop region) |
187 |
| 257/375 |
With means to reduce substrate spreading resistance (e.g., heavily doped substrate) |
67 |
| 257/377 |
With polysilicon interconnections to source or drain regions (e.g., polysilicon laminated with silicide) |
315 |
| 257/393 |
Insulated gate field effect transistor adapted to function as load element for switching insulated gate field effect transistor |
282 |
| 257/392 |
Insulated gate field effect transistors of different threshold voltages in same integrated circuit (e.g., enhancement and depletion mode) |
396 |
| 257/390 |
Matrix or array of field effect transistors (e.g., array of fets only some of which are completed, or structure for mask programmed read-only memory (rom)) |
838 |
| 257/391 |
Selected groups of complete field effect devices having different threshold voltages (e.g., different channel dopant concentrations) |
346 |
| 257/382 |
With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide) |
715 |
| 257/383 |
Contact of refractory or platinum group metal (e.g., molybdenum, tungsten, or titanium) |
303 |
| 257/384 |
Including silicide |
507 |
| 257/385 |
Multiple polysilicon layers |
153 |
| 257/394 |
With means to prevent parasitic conduction channels |
169 |
| 257/395 |
Thick insulator portion |
123 |
| 257/399 |
Combined with heavily doped channel stop portion |
102 |
| 257/396 |
Recessed into semiconductor surface |
226 |
| 257/398 |
Combined with heavily doped channel stop portion |
131 |
| 257/397 |
In vertical-walled groove |
181 |
| 257/400 |
With heavily doped channel stop portion |
92 |
| 257/386 |
With means to reduce parasitic capacitance |
155 |
| 257/387 |
Gate electrode overlaps at least one of source or drain by no more than depth of source or drain (e.g., self-aligned gate) |
168 |
| 257/388 |
Gate electrode consists of refractory or platinum group metal or silicide |
206 |
| 257/389 |
With thick insulator over source or drain region |
149 |
| 257/401 |
With specified physical layout (e.g., ring gate, source/drain regions shared between plural fets, plural sections connected in parallel to form power mosfet) |
1488 |
| 257/290 |
Light responsive or combined with light responsive device |
426 |
| 257/291 |
Imaging array |
794 |
| 257/292 |
Photodiodes accessed by fets |
926 |
| 257/293 |
Photoresistors accessed by fets, or photodetectors separate from fet chip |
159 |
| 257/294 |
With shield, filter, or lens |
305 |
| 257/327 |
Short channel insulated gate field effect transistor |
496 |
| 257/335 |
Active channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, dmos transistor) |
657 |
| 257/343 |
All contacts on same surface (e.g., lateral structure) |
431 |
| 257/337 |
In integrated circuit structure |
235 |
| 257/338 |
With complementary field effect transistor |
207 |
| 257/341 |
Plural sections connected in parallel (e.g., power mosfet) |
997 |
| 257/342 |
With means to reduce on resistance |
399 |
| 257/336 |
With lightly doped portion of drain region adjacent channel (e.g., ldd structure) |
738 |
| 257/340 |
With means (other than self-alignment of the gate electrode) to decrease gate capacitance (e.g., shield electrode) |
137 |
| 257/339 |
With means to increase breakdown voltage |
534 |
| 257/329 |
Gate controls vertical charge flow portion of channel (e.g., vmos device) |
686 |
| 257/330 |
Gate electrode in groove |
1140 |
| 257/332 |
Gate electrode self-aligned with groove |
429 |
| 257/334 |
In integrated circuit structure |
255 |
| 257/331 |
Plural gate electrodes or grid shaped gate electrode |
629 |
| 257/333 |
With thick insulator to reduce gate capacitance in non-channel areas (e.g., thick oxide over source or drain region) |
277 |
| 257/346 |
Gate electrode overlaps the source or drain by no more than depth of source or drain (e.g., self-aligned gate) |
288 |
| 257/328 |
Vertical channel or double diffused insulated gate field effect device provided with means to protect against excess voltage (e.g., gate protection diode) |
726 |
| 257/344 |
With lightly doped portion of drain region adjacent channel (e.g., ldd structure) |
970 |
| 257/345 |
With means to prevent sub-surface currents, or with non-uniform channel doping |
340 |
| 257/289 |
Significant semiconductor chemical compound in bulk crystal (e.g., gaas) |
183 |
| 257/347 |
Single crystal semiconductor layer on insulating substrate (soi) |
2367 |
| 257/348 |
Depletion mode field effect transistor |
293 |
| 257/350 |
Insulated electrode device is combined with diverse type device (e.g., complementary mosfets, fet with resistor, etc.) |
1106 |
| 257/351 |
Complementary field effect transistor structures only (i.e., not including bipolar transistors, resistors, or other components) |
688 |
| 257/352 |
Substrate is single crystal insulator (e.g., sapphire or spinel) |
306 |
| 257/353 |
Single crystal islands of semiconductor layer containing only one active device |
306 |
| 257/354 |
Including means to eliminate island edge effects (e.g., insulating filling between islands, or ions in island edges) |
285 |
| 257/349 |
With means (e.g., a buried channel stop layer) to prevent leakage current along the interface of the semiconductor layer and the insulating substrate |
477 |
| 257/314 |
Variable threshold (e.g., floating gate memory device) |
1280 |
| 257/324 |
Multiple insulator layers (e.g., mnos structure) |
834 |
| 257/325 |
Non-homogeneous composition insulator layer (e.g., graded composition layer or layer with inclusions) |
206 |
| 257/326 |
With additional, non-memory control electrode or channel portion (e.g., accessing field effect transistor structure) |
316 |
| 257/315 |
With floating gate electrode |
2010 |
| 257/316 |
With additional contacted control electrode |
1915 |
| 257/318 |
Additional control electrode is doped region in semiconductor substrate |
328 |
| 257/319 |
Plural additional contacted control electrodes |
370 |
| 257/320 |
Separate control electrodes for charging and for discharging floating electrode |
340 |
| 257/322 |
With charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction) |
251 |
| 257/317 |
With irregularities on electrode to facilitate charging or discharging of floating electrode |
549 |
| 257/321 |
With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling |
1009 |
| 257/323 |
With means to facilitate light erasure |
83 |
| 257/295 |
With ferroelectric material layer |
1701 |
| 257/409 |
With means to increase breakdown voltage (e.g., field shield electrode, guard ring, etc.) |
546 |
| 257/355 |
With overvoltage protective means |
1291 |
| 257/356 |
For protecting against gate insulator breakdown |
522 |
| 257/357 |
In complementary field effect transistor integrated circuit |
463 |
| 257/358 |
Including resistor element |
280 |
| 257/359 |
As thin film structure (e.g., polysilicon resistor) |
181 |
| 257/363 |
Including resistor element |
290 |
| 257/360 |
Protection device includes insulated gate transistor structure (e.g., combined with resistor element) |
659 |
| 257/361 |
For operation as bipolar or punchthrough element |
282 |
| 257/362 |
Punchthrough or bipolar element |
353 |
| 257/402 |
With permanent threshold adjustment (e.g., depletion mode) |
259 |
| 257/403 |
With channel conductivity dopant same type as that of source and drain |
157 |
| 257/404 |
Non-uniform channel doping |
142 |
| 257/407 |
With gate electrode of controlled workfunction material (e.g., low workfunction gate material) |
228 |
| 257/405 |
With gate insulator containing specified permanent charge |
80 |
| 257/406 |
Plural gate insulator layers |
130 |
| 257/365 |
With plural, separately connected, gate electrodes in same device |
436 |
| 257/366 |
Overlapping gate electrodes |
150 |
| 257/364 |
With resistive gate electrode |
87 |
| 257/256 |
Junction field effect transistor (unipolar transistor) |
136 |
| 257/262 |
Combined with insulated gate field effect transistor (igfet) |
114 |
| 257/259 |
Elongated active region acts as transmission line or distributed active element (e.g., "transmission line" field effect transistor) |
60 |
| 257/268 |
Enhancement mode |
62 |
| 257/269 |
With means to adjust barrier height (e.g., doping profile) |
30 |
| 257/272 |
Junction field effect transistor in integrated circuit |
152 |
| 257/274 |
Complementary junction field effect transistors |
98 |
| 257/275 |
Microwave integrated circuit (e.g., microstrip type) |
182 |
| 257/277 |
With capacitive or inductive elements |
122 |
| 257/276 |
With contact or heat sink extending through hole in semiconductor substrate, or with electrode suspended over substrate (e.g., air bridge) |
160 |
| 257/273 |
With bipolar device |
167 |
| 257/278 |
With devices vertically spaced in different layers of semiconductor material (e.g., "3-dimensional" integrated circuit) |
59 |
| 257/261 |
Junction gate region free of direct electrical connection (e.g., floating junction gate memory cell structure) |
85 |
| 257/257 |
Light responsive or combined with light responsive device |
203 |
| 257/258 |
In imaging array |
175 |
| 257/271 |
Load element or constant current source (e.g., with source to gate connection) |
34 |
| 257/270 |
Plural, separately connected, gates control same channel region |
142 |
| 257/279 |
Pn junction gate in compound semiconductor material (e.g., gaas) |
96 |
| 257/260 |
Same channel controlled by both junction and insulated gate electrodes, or by both schottky barrier and pn junction gates (e.g., "taper isolated" memory cell) |
85 |
| 257/263 |
Vertical controlled current path |
143 |
| 257/264 |
Enhancement mode or with high resistivity channel (e.g., doping of 10 15 cm -3 or less) |
138 |
| 257/265 |
In integrated circuit |
45 |
| 257/266 |
With multiple parallel current paths (e.g., grid gate) |
153 |
| 257/267 |
With schottky barrier gate |
45 |
| 257/287 |
With multiple channels or channel segments connected in parallel, or with channel much wider than length between source and drain (e.g., power jfet) |
188 |
| 257/286 |
With non-uniform channel thickness or width |
79 |
| 257/285 |
With profiled channel dopant concentration or profiled gate region dopant concentration (e.g., maximum dopant concentration below surface) |
148 |
| 257/280 |
With schottky gate |
402 |
| 257/282 |
Gate closely aligned to source region |
94 |
| 257/283 |
With groove or overhang for alignment |
98 |
| 257/284 |
Schottky gate in groove |
177 |
| 257/281 |
Schottky gate to silicon semiconductor |
104 |
| 257/252 |
Responsive to non-optical, non-electrical signal |
119 |
| 257/253 |
Chemical (e.g., isfet, chemfet) |
252 |
| 257/254 |
Physical deformation (e.g., strain sensor, acoustic wave detector) |
174 |
| 257/255 |
With current flow along specified crystal axis (e.g., axis of maximum carrier mobility) |
47 |
| 257/907 |
Folded bit line dram configuration |
71 |
| 257/202 |
Gate arrays |
415 |
| 257/204 |
Having specific type of active device (e.g., cmos) |
375 |
| 257/206 |
Particular layout of complementary fets with regard to each other |
383 |
| 257/205 |
With bipolar transistors or with fets of only one channel conductivity type (e.g., enhancement-depletion fets) |
114 |
| 257/203 |
With particular chip input/output means |
356 |
| 257/207 |
With particular power supply distribution means |
517 |
| 257/208 |
With particular signal path connections |
624 |
| 257/211 |
Multi-level metallization |
571 |
| 257/209 |
Programmable signal paths (e.g., with fuse elements, laser programmable, etc) |
417 |
| 257/210 |
With wiring channel area |
247 |
| 257/183 |
Heterojunction device |
275 |
| 257/199 |
Avalanche diode (e.g., so-called "zener" diode having breakdown voltage greater than 6 volts, including heterojunction impatt type microwave diodes) |
89 |
| 257/201 |
Between different group iv-vi or ii-vi or iii-v compounds other than gaas/gaalas |
390 |
| 257/197 |
Bipolar transistor |
738 |
| 257/198 |
Wide band gap emitter |
392 |
| 257/196 |
Both semiconductors of the heterojunction are the same conductivity type (i.e., either n or p) |
67 |
| 257/183.1 |
Charge transfer device |
57 |
| 257/192 |
Field effect transistor |
918 |
| 257/194 |
Doping on side of heterojunction with lower carrier affinity (e.g., high electron mobility transistor (hemt)) |
671 |
| 257/195 |
Combined with diverse type device |
173 |
| 257/191 |
Having graded composition |
304 |
| 257/200 |
Heterojunction formed between semiconductor materials which differ in that they belong to different periodic table groups (e.g., ge (group iv) - gaas (group iii-v) or inp (group iii-v) - cdte (group ii-vi)) |
481 |
| 257/184 |
Light responsive structure |
668 |
| 257/186 |
Avalanche photodetection structure |
203 |
| 257/188 |
Having narrow energy band gap ( |
124 |
| 257/189 |
Layer is a group iii-v semiconductor compound |
237 |
| 257/187 |
Having transistor structure |
204 |
| 257/185 |
Staircase (including graded composition) device |
159 |
| 257/190 |
With lattice constant mismatch (e.g., with buffer layer to accommodate mismatch) |
490 |
| 257/678 |
Housing or package |
1620 |
| 257/727 |
Device held in place by clamping |
590 |
| 257/708 |
Entirely of metal except for feedthrough |
136 |
| 257/711 |
With raised portion of base for mounting semiconductor chip |
142 |
| 257/709 |
With specified insulator to isolate device from housing |
118 |
| 257/710 |
With specified means (e.g., lip) to seal base to cap |
306 |
| 257/728 |
For high frequency (e.g., microwave) device |
626 |
| 257/723 |
For plural devices |
1953 |
| 257/724 |
With discrete components |
1270 |
| 257/725 |
With electrical isolation means |
285 |
| 257/726 |
Devices held in place by clamping |
251 |
| 257/687 |
Housing or package filled with solid or liquid electrically insulating material |
542 |
| 257/701 |
Insulating material |
814 |
| 257/704 |
Cap or lid |
873 |
| 257/703 |
Composite ceramic, or single ceramic with metal |
353 |
| 257/705 |
Of high thermal conductivity ceramic (e.g., beo) |
224 |
| 257/702 |
Of insulating material other than ceramic |
357 |
| 257/706 |
With heat sink |
1381 |
| 257/707 |
Directly attached to semiconductor device |
1081 |
| 257/685 |
Multiple housings |
661 |
| 257/686 |
Stacked arrangement |
1984 |
| 257/730 |
Outside periphery of package having specified shape or configuration |
632 |
| 257/729 |
Portion of housing of specific materials |
234 |
| 257/679 |
Smart (e.g., credit) card package |
482 |
| 257/690 |
With contact or lead |
1144 |
| 257/691 |
Having power distribution means (e.g., bus structure) |
1118 |
| 257/700 |
Multiple contact layers separated from each other by insulator means and forming part of a package or housing (e.g., plural ceramic layer package) |
1262 |
| 257/692 |
With particular lead geometry |
1316 |
| 257/693 |
External connection to housing |
862 |
| 257/694 |
Axial leads |
99 |
| 257/696 |
Bent (e.g., j-shaped) lead |
574 |
| 257/695 |
Fanned/radial leads |
109 |
| 257/697 |
Pin grid type |
389 |
| 257/698 |
With specific electrical feedthrough structure |
1302 |
| 257/699 |
Housing entirely of metal except for feedthrough structure |
110 |
| 257/682 |
With desiccant, getter, or gas filling |
109 |
| 257/731 |
With housing mount |
193 |
| 257/732 |
Flanged mount |
108 |
| 257/733 |
Stud mount |
81 |
| 257/688 |
With large area flexible electrodes in press contact with opposite sides of active semiconductor chip and surrounded by an insulating element, e.g., ring |
279 |
| 257/689 |
Rigid electrode portion |
158 |
| 257/683 |
With means to prevent explosion of package |
47 |
| 257/712 |
With provision for cooling the housing or its contents |
1424 |
| 257/713 |
For integrated circuit |
1240 |
| 257/720 |
Heat dissipating element has high thermal conductivity insert (e.g., copper slug in aluminum heat sink) |
527 |
| 257/718 |
Heat dissipating element held in place by clamping or spring means |
860 |
| 257/719 |
Pressed against semiconductor element |
1043 |
| 257/717 |
Isolation of cooling means (e.g., heat sink) by an electrically insulating element (e.g., spacer) |
609 |
| 257/714 |
Liquid coolant |
822 |
| 257/715 |
Boiling (evaporative) liquid |
511 |
| 257/716 |
Cryogenic liquid coolant |
77 |
| 257/721 |
With gas coolant |
156 |
| 257/722 |
With fins |
774 |
| 257/684 |
With semiconductor element forming part (e.g., base, of housing) |
544 |
| 257/680 |
With window means |
624 |
| 257/681 |
For erasing eprom |
65 |
| 257/617 |
Including region containing crystal damage |
194 |
| 257/613 |
Including semiconductor material other than silicon or gallium arsenide (gaas) (e.g., pb x sn 1-x te) |
209 |
| 257/616 |
Containing germanium, ge |
339 |
| 257/614 |
Group ii-vi compound (e.g., cdte, hg x cd 1-x te) |
108 |
| 257/615 |
Group iii-v compound (e.g., inp) |
267 |
| 257/79 |
Incoherent light emitter structure |
1144 |
| 257/86 |
Active layer of indirect band gap semiconductor |
160 |
| 257/87 |
With means to facilitate electron-hole recombination (e.g., isoelectronic traps such as nitrogen in gap) |
91 |
| 257/100 |
Encapsulated |
665 |
| 257/80 |
In combination with or also constituting light responsive device |
470 |
| 257/84 |
Combined in integrated structure |
336 |
| 257/85 |
With heterojunction |
242 |
| 257/83 |
Light coupled transistor structure |
208 |
| 257/81 |
With specific housing or contact structure |
663 |
| 257/82 |
Discrete light emitting and light responsive devices |
549 |
| 257/88 |
Plural light emitting devices (e.g., matrix, 7-segment array) |
758 |
| 257/92 |
Alphanumeric segmented array |
48 |
| 257/89 |
Multi-color emission |
353 |
| 257/90 |
With heterojunction |
128 |
| 257/93 |
With electrical isolation means in integrated circuit structure |
173 |
| 257/91 |
With shaped contacts or opaque masking |
252 |
| 257/94 |
With heterojunction |
994 |
| 257/96 |
Plural heterojunctions in same device |
654 |
| 257/97 |
More than two heterojunctions in same device |
452 |
| 257/95 |
With contoured external surface (e.g., dome shape to facilitate light emission) |
323 |
| 257/99 |
With housing or contact structure |
1599 |
| 257/101 |
With particular dopant concentration or concentration profile (e.g., graded junction) |
343 |
| 257/102 |
With particular dopant material (e.g., zinc as dopant in gaas) |
460 |
| 257/103 |
With particular semiconductor material |
1709 |
| 257/98 |
With reflector, opaque mask, or optical element (e.g., lens, optical fiber, index of refraction matching layer, luminescent material layer, filter) integral with device or device enclosure or package |
1953 |
| 257/499 |
Integrated circuit structure with electrically isolated components |
321 |
| 257/506 |
Including dielectric isolation means |
785 |
| 257/522 |
Air isolation (e.g., beam lead supported semiconductor islands) |
289 |
| 257/509 |
Combined with pn junction isolation (e.g., isoplanar, locos) |
186 |
| 257/510 |
Dielectric in groove |
697 |
| 257/520 |
Conductive filling in dielectric-lined groove (e.g., polysilicon backfill) |
266 |
| 257/519 |
Including heavily doped channel stop region adjacent groove |
157 |
| 257/521 |
Sides of grooves along major crystal planes (e.g., (111), (100) planes, etc.) |
67 |
| 257/513 |
Vertical walled groove |
311 |
| 257/514 |
With active junction abutting groove (e.g., "walled emitter") |
119 |
| 257/515 |
With active junction abutting groove (e.g., "walled emitter") |
108 |
| 257/517 |
With bipolar transistor structure |
237 |
| 257/518 |
With polycrystalline connecting region (e.g., polysilicon base contact) |
171 |
| 257/511 |
With complementary (npn and pnp) bipolar transistor structures |
134 |
| 257/512 |
Complementary devices share common active region (e.g., integrated injection logic, i 2 l) |
70 |
| 257/516 |
With passive component (e.g., resistor, capacitor, etc.) |
210 |
| 257/524 |
Full dielectric isolation with polycrystalline semiconductor substrate |
155 |
| 257/525 |
With complementary (npn and pnp) bipolar transistor structures |
61 |
| 257/523 |
Isolation by region of intrinsic (undoped) semiconductor material (e.g., including region physically damaged by proton bombardment) |
83 |
| 257/526 |
With bipolar transistor structure |
130 |
| 257/527 |
Sides of isolated semiconductor islands along major crystal planes (e.g., (111), (100) planes, etc.) |
34 |
| 257/508 |
With metallic conductor within isolating dielectric or between semiconductor and isolating dielectric (e.g., metal shield layer or internal connection layer) |
345 |
| 257/507 |
With single crystal insulating substrate (e.g., sapphire) |
115 |
| 257/500 |
Including high voltage or high power devices isolated from low voltage or low power devices in the same integrated circuit |
315 |
| 257/502 |
High power or high voltage device extends completely through semiconductor substrate (e.g., backside collector contact) |
119 |
| 257/501 |
Including dielectric isolation means |
269 |
| 257/504 |
Including means for establishing a depletion region throughout a semiconductor layer for isolating devices in different portions of the layer (e.g., "jfet" isolation) |
50 |
| 257/557 |
Lateral bipolar transistor structure |
228 |
| 257/559 |
With active region formed along groove or exposed edge in semiconductor |
73 |
| 257/558 |
With base region doping concentration step or gradient or with means to increase current gain |
61 |
| 257/560 |
With multiple collectors or emitters |
91 |
| 257/562 |
With auxiliary collector/re-emitter between emitter and output collector (e.g., "current hogging logic" device) |
24 |
| 257/561 |
With different emitter to collector spacings or facing areas |
44 |
| 257/528 |
Passive components in ics |
488 |
| 257/532 |
Including capacitor component |
1284 |
| 257/535 |
Both terminals of capacitor isolated from substrate |
213 |
| 257/533 |
Combined with resistor to form rc filter structure |
160 |
| 257/534 |
With means to increase surface area (e.g., grooves, ridges, etc.) |
210 |
| 257/531 |
Including inductive element |
513 |
| 257/529 |
Including programmable passive component (e.g., fuse) |
779 |
| 257/530 |
Anti-fuse |
638 |
| 257/536 |
Including resistive element |
556 |
| 257/539 |
Combined with bipolar transistor |
126 |
| 257/543 |
Lightly doped junction isolated resistor (e.g., ion implanted resistor) |
42 |
| 257/541 |
Pinch resistor |
42 |
| 257/542 |
Resistor has same doping as emitter or collector of bipolar transistor |
33 |
| 257/540 |
With compensation for non-linearity (e.g., dynamic isolation pocket bias) |
22 |
| 257/537 |
Using specific resistive material |
267 |
| 257/538 |
Polycrystalline silicon (doped or undoped) |
267 |
| 257/503 |
With contact or metallization configuration to reduce parasitic coupling (e.g., separate ground pads for different parts of integrated circuit) |
185 |
| 257/563 |
With multiple separately connected emitter, collector, or base regions in same transistor structure |
87 |
| 257/564 |
Multiple base or collector regions |
64 |
| 257/544 |
With pn junction isolation |
202 |
| 257/548 |
At least three regions of alternating conductivity types with dopant concentration gradients decreasing from surface of semiconductor (e.g., "triple-diffused" integrated circuit) |
68 |
| 257/551 |
Including voltage reference element (e.g., avalanche diode, so-called "zener diode" with breakdown voltage greater than 6 volts or with positive temperature coefficient of breakdown voltage) |
140 |
| 257/552 |
With bipolar transistor structure |
197 |
| 257/555 |
Complementary bipolar transistor structures (e.g., integrated injection logic, i 2 l) |
104 |
| 257/556 |
Including lateral bipolar transistor structure |
119 |
| 257/553 |
Transistors of same conductivity type (e.g., npn) having different current gain or different operating voltage characteristics |
37 |
| 257/554 |
With connecting region made of polycrystalline semiconductor material (e.g., polysilicon base contact) |
60 |
| 257/550 |
With lightly doped surface layer of one conductivity type on substrate of opposite conductivity type, having plural heavily doped portions of the one conductivity type between the layer and substrate, different ones of the heavily doped portions having differing depths or physical extent |
61 |
| 257/545 |
With means to control isolation junction capacitance (e.g., lightly doped layer at isolation junction to increase depletion layer width) |
36 |
| 257/547 |
With structural means to control parasitic transistor action or leakage current |
147 |
| 257/546 |
With structural means to protect against excess or reversed polarity voltage |
227 |
| 257/549 |
With substrate and lightly doped surface layer of same conductivity type, separated by subsurface heavily doped region of opposite conductivity type (e.g., "collector diffused isolation" integrated circuit) |
84 |
| 257/505 |
With polycrystalline semiconductor isolation region in direct contact with single crystal active semiconductor material |
74 |
| 257/666 |
Lead frame |
2175 |
| 257/677 |
Of specified material other than copper (e.g., kovar (t.m.)) |
200 |
| 257/668 |
On insulating carrier other than a printed circuit board |
984 |
| 257/672 |
Small lead frame (e.g., "spider" frame) for connecting a large lead frame to a semiconductor chip |
343 |
| 257/673 |
With bumps on ends of lead fingers to connect to semiconductor |
432 |
| 257/667 |
With dam or vent for encapsulant |
356 |
| 257/675 |
With heat sink means |
635 |
| 257/674 |
With means for controlling lead tension |
275 |
| 257/670 |
With separate tie bar element or plural tie bars |
385 |
| 257/671 |
Of insulating material |
127 |
| 257/669 |
With stress relief |
474 |
| 257/676 |
With structure for mounting semiconductor chip to lead frame (e.g., configuration of die bonding flag, absence of a die bonding flag, recess for led) |
1651 |
| 257/918 |
Light emitting regenerative switching device (e.g., light emitting scr) arrays, circuitry, etc. |
73 |
| 257/E33.001 |
Light emitting semiconductor devices having a potential or a surface barrier, processes or apparatus peculiar to the manufacture or treatment of such devices, or of parts thereof |
113 |
| 257/E33.055 |
Detail of nonsemiconductor component other than light-emitting semiconductor device (epo) |
21 |
| 257/E33.06 |
Coatings (epo) |
158 |
| 257/E33.061 |
Comprising luminescent material (e.g., fluorescent) (epo) |
323 |
| 257/E33.066 |
Electrical contact or lead (e.g., lead frame) (epo) |
346 |
| 257/E33.062 |
Electrodes (epo) |
51 |
| 257/E33.063 |
Characterized by material (epo) |
290 |
| 257/E33.064 |
Comprising transparent conductive layers (e.g., transparent conductive oxides (tco), indium tin oxide (ito)) (epo) |
149 |
| 257/E33.065 |
Characterized by shape (epo) |
296 |
| 257/E33.067 |
Means for light extraction or guiding (epo) |
220 |
| 257/E33.068 |
Integrated with device (e.g., back surface reflector, lens) (epo) |
360 |
| 257/E33.069 |
Comprising resonant cavity structure (e.g., bragg reflector pair) (epo) |
162 |
| 257/E33.07 |
Comprising window layer (epo) |
114 |
| 257/E33.071 |
Not integrated with device (epo) |
30 |
| 257/E33.072 |
Reflective means (epo) |
199 |
| 257/E33.073 |
Refractive means (e.g., lens) (epo) |
133 |
| 257/E33.074 |
Scattering means (e.g., surface roughening) (epo) |
112 |
| 257/E33.077 |
Monolithic integration with photosensitive device (epo) |
12 |
| 257/E33.056 |
Packaging (epo) |
118 |
| 257/E33.057 |
Adapted for surface mounting (epo) |
209 |
| 257/E33.059 |
Encapsulation (epo) |
322 |
| 257/E33.058 |
Housing (epo) |
180 |
| 257/E33.075 |
With means for cooling or heating (epo) |
272 |
| 257/E33.076 |
With means for light detecting (e.g., photodetector) (epo) |
116 |
| 257/E33.002 |
Device characterized by semiconductor body (epo) |
17 |
| 257/E33.013 |
Material of active region (epo) |
14 |
| 257/E33.037 |
Comprising compound other than group ii-vi, iii-v, and iv compound (epo) |
22 |
| 257/E33.041 |
Characterized by doping material (epo) |
4 |
| 257/E33.04 |
Comprising only group i-iii-vi compound (epo) |
12 |
| 257/E33.039 |
Comprising only group ii-iv-vi compound (epo) |
1 |
| 257/E33.038 |
Comprising only group iv-vi compound (epo) |
3 |
| 257/E33.042 |
Comprising only group iv-vi or ii-iv-vi compound (epo) |
0 |
| 257/E33.019 |
Comprising only group ii-vi compound (epo) |
58 |
| 257/E33.022 |
Characterized by doping material (epo) |
58 |
| 257/E33.02 |
Ternary or quaternary compound (e.g., cdhgte) (epo) |
24 |
| 257/E33.021 |
With heterojunction (epo) |
95 |
| 257/E33.023 |
Comprising only group iii-v compound (epo) |
29 |
| 257/E33.024 |
Binary compound (e.g., gaas) (epo) |
30 |
| 257/E33.025 |
Including nitride (e.g., gan) (epo) |
78 |
| 257/E33.029 |
Characterized by doping material (epo) |
118 |
| 257/E33.03 |
Nitride compound (epo) |
101 |
| 257/E33.031 |
Including ternary or quaternary compound (e.g., algaas) (epo) |
5 |
| 257/E33.033 |
Comprising nitride compound (e.g., algan) (epo) |
20 |
| 257/E33.034 |
With heterojunction (e.g., algan/gan) (epo) |
34 |
| 257/E33.032 |
With heterojunction (e.g., algaas/gaas) (epo) |
15 |
| 257/E33.026 |
Ternary or quaternary compound (e.g., algaas) (epo) |
45 |
| 257/E33.028 |
Including nitride (e.g., algan) (epo) |
571 |
| 257/E33.027 |
With heterojunction (epo) |
289 |
| 257/E33.035 |
Comprising only group iv compound (e.g., sic) (epo) |
46 |
| 257/E33.036 |
Characterized by doping material (epo) |
8 |
| 257/E33.015 |
Comprising only group iv element (epo) |
52 |
| 257/E33.017 |
Characterized by doping material (epo) |
23 |
| 257/E33.018 |
Including porous si (epo) |
73 |
| 257/E33.016 |
With heterojunction (epo) |
16 |
| 257/E33.014 |
In different regions (epo) |
3 |
| 257/E33.003 |
Particular crystalline orientation or structure (epo) |
122 |
| 257/E33.004 |
Comprising amorphous semiconductor (epo) |
59 |
| 257/E33.043 |
Physical imperfections (e.g., particular concentration or distribution of impurity) (epo) |
135 |
| 257/E33.005 |
Shape or structure (e.g., shape of epitaxial layer) (epo) |
277 |
| 257/E33.011 |
For current confinement (epo) |
78 |
| 257/E33.012 |
Multiple active regions between two electrodes (e.g., stacks) (epo) |
101 |
| 257/E33.008 |
Multiple quantum well structure (epo) |
317 |
| 257/E33.01 |
Doped superlattice (e.g., nipi superlattice) (epo) |
8 |
| 257/E33.009 |
Including, apart from doping materials or other only impurities, group iv element (e.g., si-sige superlattice) (epo) |
22 |
| 257/E33.007 |
Shape of potential barrier (epo) |
114 |
| 257/E33.006 |
Shape of semiconductor body (epo) |
241 |
| 257/E33.044 |
Device characterized by their operation (epo) |
48 |
| 257/E33.053 |
Characterized by field-effect operation (epo) |
13 |
| 257/E33.054 |
Device being superluminescent diode (epo) |
58 |
| 257/E33.048 |
Having heterojunction or graded gap (epo) |
33 |
| 257/E33.05 |
Comprising only group ii-iv compound (epo) |
8 |
| 257/E33.049 |
Comprising only group iii-v compound (epo) |
213 |
| 257/E33.052 |
Having mis barrier layer (epo) |
22 |
| 257/E33.045 |
Having p-n or hi-lo junction (epo) |
100 |
| 257/E33.047 |
Having at least two p-n junctions (epo) |
45 |
| 257/E33.046 |
P-i-n device (epo) |
27 |
| 257/E33.051 |
Having schottky barrier (epo) |
19 |
| 257/911 |
Light sensitive array adapted to be scanned by electron beam (e.g.,vidicon device) |
29 |
| 257/909 |
Macrocell arrays (e.g., gate arrays with variable size or configuration of cells) |
87 |
| 257/798 |
Miscellaneous |
179 |
| 257/901 |
Mosfet substrate bias |
75 |
| 257/900 |
Mosfet type gate sidewall insulating spacer |
445 |
| 257/916 |
Narrow band gap semiconductor material (>>1ev) |
42 |
| 257/49 |
Non-single crystal, or recrystallized, semiconductor material forms part of active junction (including field-induced active junction) |
218 |
| 257/52 |
Amorphous semiconductor material |
271 |
| 257/63 |
Amorphous semiconductor is alloy or contains material to change band gap (e.g., si x ge 1-x , sin y ) |
144 |
| 257/57 |
Field effect device in amorphous semiconductor material |
509 |
| 257/59 |
In array having structure for use as imager or display, or with transparent electrode |
2179 |
| 257/60 |
With field electrode under or on a side edge of amorphous semiconductor material (e.g., vertical current path) |
119 |
| 257/61 |
With heavily doped regions contacting amorphous semiconductor material (e.g., heavily doped source and drain) |
152 |
| 257/58 |
With impurity other than hydrogen to passivate dangling bonds (e.g., halide) |
61 |
| 257/53 |
Responsive to nonelectrical external signals (e.g., light) |
483 |
| 257/55 |
Amorphous semiconductor is alloy or contains material to change band gap (e.g., si x ge 1-x , sin y ) |
216 |
| 257/56 |
With impurity other than hydrogen to passivate dangling bonds (e.g., halide) |
120 |
| 257/54 |
With schottky barrier to amorphous material |
76 |
| 257/62 |
With impurity other than hydrogen to passivate dangling bonds (e.g., halide) |
57 |
| 257/66 |
Field effect device in non-single crystal, or recrystallized, semiconductor material |
983 |
| 257/72 |
In array having structure for use as imager or display, or with transparent electrode |
2110 |
| 257/71 |
In combination with capacitor element (e.g., dram) |
233 |
| 257/67 |
In combination with device formed in single crystal semiconductor material (e.g., stacked fets) |
305 |
| 257/68 |
Capacitor element in single crystal semiconductor (e.g., dram) |
227 |
| 257/69 |
Field effect transistor in single crystal material, complementary to that in non-single crystal, or recrystallized, material (e.g., cmos) |
324 |
| 257/70 |
Recrystallized semiconductor material |
159 |
| 257/50 |
Non-single crystal, or recrystallized, active junction adapted to be electrically shorted (e.g., "anti-fuse" element) |
271 |
| 257/65 |
Non-single crystal, or recrystallized, material containing non-dopant additive, or alloy of semiconductor materials (e.g., ge x si 1- x, polycrystalline silicon with dangling bond modifier) |
254 |
| 257/51 |
Non-single crystal, or recrystallized, material forms active junction with single crystal material (e.g., monocrystal to polycrystal pn junction or heterojunction) |
187 |
| 257/64 |
Non-single crystal, or recrystallized, material with specified crystal structure (e.g., specified crystal size or orientation) |
315 |
| 257/74 |
Plural recrystallized semiconductor layers (e.g., "3-dimensional integrated circuit") |
121 |
| 257/75 |
Recrystallized semiconductor material |
180 |
| 257/73 |
Schottky barrier to polycrystalline semiconductor material |
61 |
| 257/40 |
Organic semiconductor material |
1711 |
| 257/E51.001 |
Organic solid state devices, processes or apparatus peculiar to manufacture or treatment of such devices or of parts thereof |
50 |
| 257/E51.024 |
Selection of material for organic solid-state device (epo) |
16 |
| 257/E51.045 |
Biomolecule or macromolecule (e.g., proteins, atp, chlorophyl, beta-carotene, lipids, enzymes) (epo) |
29 |
| 257/E51.038 |
Carbon-containing materials (epo) |
26 |
| 257/E51.04 |
Carbon nanotubes (epo) |
142 |
| 257/E51.039 |
Fullerenes (epo) |
48 |
| 257/E51.041 |
Coordination compound (e.g., porphyrin, phthalocyanine, metal(ii) polypyridine complexes) (epo) |
278 |
| 257/E51.043 |
Metal complexes comprising group iiib metal (al, ga, in, or ti) (e.g., tris (8-hydroxyquinoline) aluminium (alq3)) (epo) |
399 |
| 257/E51.042 |
Phthalocyanine (epo) |
186 |
| 257/E51.044 |
Transition metal complexes (e.g., ru(ii) polypyridine complexes) (epo) |
252 |
| 257/E51.025 |
For organic solid-state device adapted for rectifying, amplifying, oscillating, or switching, or capacitors or resistors with potential or surface barrier (epo) |
4 |
| 257/E51.026 |
For radiation-sensitive or light-emitting organic solid-state device with potential or surface barrier (epo) |
18 |
| 257/E51.052 |
Langmuir blodgett film (epo) |
7 |
| 257/E51.047 |
Macromolecular system with low molecular weight (e.g., cyanine dyes, coumarine dyes, tetrathiafulvalene) (epo) |
405 |
| 257/E51.051 |
Amine compound having at least two aryl on amine-nitrogen atom (e.g., triphenylamine) (epo) |
579 |
| 257/E51.048 |
Charge transfer complexes (epo) |
59 |
| 257/E51.049 |
Polycondensed aromatic or heteroaromatic compound (e.g., pyrene, perylene, pentacene) (epo) |
418 |
| 257/E51.05 |
Aromatic compound containing heteroatom (e.g., perylenetetracarboxylic dianhydride, perylene tetracarboxylic diimide) (epo) |
153 |
| 257/E51.027 |
Organic polymer or oligomer (epo) |
35 |
| 257/E51.033 |
Comprising aliphatic or olefinic chains (e.g., polyn-vinylcarbazol, pvc, ptfe) (epo) |
92 |
| 257/E51.034 |
Polyacetylene or derivatives (epo) |
30 |
| 257/E51.035 |
Polyn-vinylcarbazol and derivative (epo) |
94 |
| 257/E51.028 |
Comprising aromatic, heteroaromatic, or arrylic chains (e.g., polyaniline, polyphenylene, polyphenylene vinylene) (epo) |
269 |
| 257/E51.029 |
Heteroaromatic compound comprising sulfur or selene (e.g., polythiophene) (epo) |
276 |
| 257/E51.03 |
Polyethylene dioxythiophene and derivative (epo) |
133 |
| 257/E51.032 |
Polyflurorene and derivative (epo) |
139 |
| 257/E51.031 |
Polyphenylenevinylene and derivatives (epo) |
219 |
| 257/E51.036 |
Copolymers (epo) |
175 |
| 257/E51.037 |
Ladder-type polymer (epo) |
31 |
| 257/E51.046 |
Silicon-containing organic semiconductor (epo) |
97 |
| 257/E51.002 |
Structural detail of device (epo) |
4 |
| 257/E51.018 |
Light-emitting organic solid-state device with potential or surface barrier (epo) |
245 |
| 257/E51.019 |
Electrode (epo) |
36 |
| 257/E51.021 |
Arrangements for extracting light from device (e.g., bragg reflector pair) (epo) |
13 |
| 257/E51.02 |
Encapsulation (epo) |
20 |
| 257/E51.022 |
Multicolor organic light-emitting device (oled) (epo) |
80 |
| 257/E51.023 |
Molecular electronic device (epo) |
125 |
| 257/E51.003 |
Organic solid-state device adapted for rectifying, amplifying, oscillating, or switching, or capacitors or resistors with potential or surface barrier (epo) |
16 |
| 257/E51.004 |
Controllable by only signal applied to control electrode (e.g., base of bipolar transistor, gate of field-effect transistor) (epo) |
28 |
| 257/E51.005 |
Field-effect device (e.g., tft, fet) (epo) |
166 |
| 257/E51.006 |
Insulated gate field-effect transistor (epo) |
162 |
| 257/E51.007 |
Comprising organic gate dielectric (epo) |
82 |
| 257/E51.008 |
Controllable only by variation of electric current supplied or only electric potential applied to electrode carrying current to be rectified, amplified, oscillated, or switched (e.g., two terminal device) (epo) |
9 |
| 257/E51.011 |
Comprising organic/inorganic heterojunction (epo) |
18 |
| 257/E51.01 |
Comprising organic/organic junction (e.g., heterojunction) (epo) |
10 |
| 257/E51.009 |
Comprising schottky junction (epo) |
9 |
| 257/E51.012 |
Radiation-sensitive organic solid-state device (epo) |
96 |
| 257/E51.014 |
Comprising bulk heterojunction (epo) |
30 |
| 257/E51.017 |
Comprising organic semiconductor-organic semiconductor heterojunction (epo) |
52 |
| 257/E51.015 |
Comprising organic/inorganic heterojunction (epo) |
9 |
| 257/E51.016 |
Majority carrier device using sensitization of wide band gap semiconductor (e.g., tio 2 ) (epo) |
37 |
| 257/E51.013 |
Metal-organic semiconductor-metal device (epo) |
25 |
| 257/E23.001 |
Packaging, interconnects, and markings for semiconductor or other solid-state devices (epo) |
86 |
| 257/E23.01 |
Arrangements for conducting electric current to or from solid-state body in operation, e.g., leads, terminal arrangements (epo) |
161 |
| 257/E23.012 |
Consisting of lead-in layers inseparably applied to semiconductor body (epo) |
47 |
| 257/E23.014 |
Beam leads (epo) |
56 |
| 257/E23.013 |
Bridge structure with air gap (epo) |
94 |
| 257/E23.019 |
Consisting of layered constructions comprising conductive layers and insulating layers, e.g., planar contacts (epo) |
816 |
| 257/E23.02 |
Bonding areas, e.g., pads (epo) |
979 |
| 257/E23.021 |
Bump or ball contacts (epo) |
1585 |
| 257/E23.022 |
Overhang structure (epo) |
18 |
| 257/E23.016 |
For devices consisting of semiconductor layers on insulating or semi-insulating substrates, e.g., silicon on sapphire devices, i.e., sos (epo) |
71 |
| 257/E23.017 |
Materials (epo) |
79 |
| 257/E23.018 |
Conductive organic material or pastes, e.g., conductive adhesives, inks (epo) |
112 |
| 257/E23.015 |
Pads with extended contours, e.g., grid structure, branch structure, finger structure (epo) |
233 |
| 257/E23.023 |
Consisting of soldered or bonded constructions (epo) |
124 |
| 257/E23.026 |
Bases or plates or solder therefor (epo) |
89 |
| 257/E23.028 |
Characterized by material (epo) |
66 |
| 257/E23.03 |
Carbon (epo) |
19 |
| 257/E23.029 |
Semiconductor (epo) |
8 |
| 257/E23.027 |
Having heterogeneous or anisotropic structure (epo) |
37 |
| 257/E23.031 |
Lead frames or other flat leads (epo) |
182 |
| 257/E23.032 |
Additional leads (epo) |
62 |
| 257/E23.033 |
Additional leads being bump or wire (epo) |
104 |
| 257/E23.035 |
Additional leads being multilayer (epo) |
39 |
| 257/E23.034 |
Additional leads being tape carrier or flat leads (epo) |
124 |
| 257/E23.036 |
Additional leads being wiring board (epo) |
178 |
| 257/E23.052 |
Assembly of semiconductor devices on lead frame (epo) |
558 |
| 257/E23.058 |
Battery in combination with lead frame (epo) |
19 |
| 257/E23.057 |
Capacitor integral with or on lead frame (epo) |
103 |
| 257/E23.037 |
Characterized by die pad (epo) |
420 |
| 257/E23.039 |
Chip-on-leads or leads-on-chip techniques, i.e., inner lead fingers being used as die pad (epo) |
991 |
| 257/E23.04 |
Having bonding material between chip and die pad (epo) |
178 |
| 257/E23.038 |
Insulative substrate being used as die pad, e.g., ceramic, plastic (epo) |
56 |
| 257/E23.053 |
Characterized by materials of lead frames or layers thereon (epo) |
109 |
| 257/E23.054 |
Metallic layers on lead frames (epo) |
282 |
| 257/E23.055 |
Consisting of thin flexible metallic tape with or without film carrier (epo) |
514 |
| 257/E23.043 |
Geometry of lead frame (epo) |
585 |
| 257/E23.046 |
Cross-section geometry (epo) |
354 |
| 257/E23.047 |
Characterized by bent parts (epo) |
223 |
| 257/E23.048 |
Bent parts being outer leads (epo) |
202 |
| 257/E23.045 |
Deformation absorbing parts in lead frame plane, e.g., meanderline shape (epo) |
53 |
| 257/E23.044 |
For devices adapted for rectifying, amplifying, oscillating, or switching, capacitors, or resistors with at least one potential-jump barrier or surface barrier (epo) |
416 |
| 257/E23.049 |
Insulating layers on lead frame, e.g., bridging members (epo) |
196 |
| 257/E23.05 |
Side rails of lead frame, e.g., with perforations, sprocket holes (epo) |
43 |
| 257/E23.056 |
Insulating layers on lead frames (epo) |
71 |
| 257/E23.041 |
Multilayer (epo) |
75 |
| 257/E23.059 |
Oscillators in combination with lead frame (epo) |
15 |
| 257/E23.042 |
Plurality of lead frames mounted in one device (epo) |
170 |
| 257/E23.051 |
Specifically adapted to facilitate heat dissipation (epo) |
209 |
| 257/E23.06 |
Leads, i.e., metallizations or lead frames on insulating substrates, e.g., chip carriers (epo) |
172 |
| 257/E23.068 |
Additional leads joined to metallizations on insulating substrate, e.g., pins, bumps, wires, flat leads (epo) |
710 |
| 257/E23.069 |
Spherical bumps on substrate for external connection, e.g., ball grid arrays (bga) (epo) |
1362 |
| 257/E23.072 |
Characterized by materials (epo) |
211 |
| 257/E23.074 |
Carbon, e.g., fullerenes (epo) |
10 |
| 257/E23.075 |
Conductive materials containing organic materials or pastes, e.g., for thick films (epo) |
319 |
| 257/E23.073 |
Conductive materials containing semiconductor material (epo) |
14 |
| 257/E23.076 |
Conductive materials containing superconducting material (epo) |
31 |
| 257/E23.077 |
Materials of insulating layers or coatings (epo) |
412 |
| 257/E23.063 |
Chip support structure consisting of plurality of insulating substrates (epo) |
283 |
| 257/E23.065 |
Flexible insulating substrates (epo) |
712 |
| 257/E23.064 |
For flat cards, e.g., credit cards (epo) |
200 |
| 257/E23.07 |
Geometry or layout (epo) |
784 |
| 257/E23.071 |
For devices adapted for rectifying, amplifying, oscillating, or switching, capacitors, or resistors with at least one potential-jump barrier or surface barrier (epo) |
33 |
| 257/E23.066 |
Lead frames fixed on or encapsulated in insulating substrates (epo) |
315 |
| 257/E23.061 |
Leads being also applied on sidewalls or bottom of substrate, e.g., leadless packages for surface mounting (epo) |
308 |
| 257/E23.062 |
Multilayer substrates (epo) |
563 |
| 257/E23.067 |
Via connections through substrates, e.g., pins going through substrate, coaxial cables (epo) |
1173 |
| 257/E23.024 |
Wire-like arrangements or pins or rods (epo) |
172 |
| 257/E23.025 |
Characterized by materials of wires or their coatings (epo) |
132 |
| 257/E23.078 |
Flexible arrangements, e.g., pressure contacts without soldering (epo) |
438 |
| 257/E23.079 |
For integrated circuit devices, e.g., power bus, number of leads (epo) |
804 |
| 257/E23.011 |
Internal lead connections, e.g., via connections, feedthrough structures (epo) |
552 |
| 257/E23.141 |
Arrangements for conducting electric current within device in operation from one component to another, interconnections, e.g., wires, lead frames (epo) |
155 |
| 257/E23.142 |
Including external interconnections consisting of multilayer structure of conductive and insulating layers inseparably formed on semiconductor body (epo) |
354 |
| 257/E23.144 |
Capacitive arrangements or effects of, or between wiring layers (epo) |
784 |
| 257/E23.154 |
Characterized by materials (epo) |
55 |
| 257/E23.155 |
Conductive materials (epo) |
3 |
| 257/E23.157 |
Based on metals, e.g., alloys, metal silicides (epo) |
67 |
| 257/E23.158 |
Principal metal being aluminum (epo) |
49 |
| 257/E23.16 |
Additional layers associated with aluminum layers, e.g., adhesion, barrier, cladding layers (epo) |
696 |
| 257/E23.159 |
Aluminum alloys (epo) |
109 |
| 257/E23.161 |
Principal metal being copper (epo) |
169 |
| 257/E23.162 |
Principal metal being noble metal, e.g., gold (epo) |
138 |
| 257/E23.163 |
Principal metal being refractory metal (epo) |
206 |
| 257/E23.165 |
Containing carbon, e.g., fullerenes (epo) |
20 |
| 257/E23.166 |
Containing conductive organic materials or pastes, e.g., conductive adhesives, inks (epo) |
65 |
| 257/E23.164 |
Containing semiconductor material, e.g., polysilicon (epo) |
270 |
| 257/E23.156 |
Containing superconducting materials (epo) |
38 |
| 257/E23.167 |
Insulating materials (epo) |
1090 |
| 257/E23.143 |
Crossover interconnections (epo) |
90 |
| 257/E23.151 |
Geometry or layout of interconnection structure (epo) |
579 |
| 257/E23.153 |
Arrangements of power or ground buses (epo) |
329 |
| 257/E23.152 |
Cross-sectional geometry (epo) |
328 |
| 257/E23.145 |
Via connections in multilevel interconnection structure (epo) |
1109 |
| 257/E23.146 |
With adaptable interconnections (epo) |
209 |
| 257/E23.147 |
Comprising antifuses, i.e., connections having their state changed from nonconductive to conductive (epo) |
470 |
| 257/E23.148 |
Change of state resulting from use of external beam, e.g., laser beam or ion beam (epo) |
73 |
| 257/E23.149 |
Comprising fuses, i.e., connections having their state changed from conductive to nonconductive (epo) |
404 |
| 257/E23.15 |
Change of state resulting from use of external beam, e.g., laser beam or ion beam (epo) |
427 |
| 257/E23.168 |
Including internal interconnections, e.g., cross-under constructions (epo) |
138 |
| 257/E23.169 |
Interconnection structure between plurality of semiconductor chips being formed on or in insulating substrates (epo) |
213 |
| 257/E23.171 |
Adaptable interconnections, e.g., for engineering changes (epo) |
220 |
| 257/E23.172 |
Assembly of plurality of insulating substrates (epo) |
414 |
| 257/E23.178 |
Chips being integrally enclosed by interconnect and support structures (epo) |
370 |
| 257/E23.174 |
Conductive vias through substrate with or without pins, e.g., buried coaxial conductors (epo) |
279 |
| 257/E23.17 |
Crossover interconnections, e.g., bridge stepovers (epo) |
64 |
| 257/E23.177 |
Flexible insulating substrates (epo) |
287 |
| 257/E23.176 |
For flat cards, e.g., credit cards (epo) |
64 |
| 257/E23.175 |
Geometry or layout of interconnection structure (epo) |
215 |
| 257/E23.173 |
Multilayer substrates (epo) |
418 |
| 257/E23.08 |
Arrangements for cooling, heating, ventilating or temperature compensation; temperature-sensing arrangements (epo) |
243 |
| 257/E23.081 |
Arrangements for heating (epo) |
68 |
| 257/E23.095 |
Complete device being wholly immersed in fluid other than air (epo) |
29 |
| 257/E23.096 |
Fluid being liquefied gas, e.g., in cryogenic vessel (epo) |
54 |
| 257/E23.082 |
Cooling arrangements using peltier effect (epo) |
140 |
| 257/E23.087 |
Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling (epo) |
192 |
| 257/E23.09 |
Auxiliary members in containers characterized by their shape, e.g., pistons (epo) |
258 |
| 257/E23.092 |
Auxiliary members in encapsulations (epo) |
814 |
| 257/E23.091 |
Bellows (epo) |
38 |
| 257/E23.093 |
In combination with jet impingement (epo) |
30 |
| 257/E23.094 |
Pistons, e.g., spring-loaded members (epo) |
112 |
| 257/E23.088 |
Cooling by change of state, e.g., use of heat pipes (epo) |
625 |
| 257/E23.089 |
By melting or evaporation of solids (epo) |
68 |
| 257/E23.097 |
Involving transfer of heat by flowing fluids (epo) |
16 |
| 257/E23.099 |
By flowing gases, e.g., air (epo) |
764 |
| 257/E23.1 |
Jet impingement (epo) |
73 |
| 257/E23.098 |
By flowing liquids (epo) |
580 |
| 257/E23.083 |
Mountings or securing means for detachable cooling or heating arrangements; fixed by friction, plugs or springs (epo) |
83 |
| 257/E23.086 |
Snap-on arrangements, e.g., clips (epo) |
721 |
| 257/E23.084 |
With bolts or screws (epo) |
475 |
| 257/E23.085 |
For stacked arrangements of plurality of semiconductor devices (epo) |
91 |
| 257/E23.101 |
Selection of materials, or shaping, to facilitate cooling or heating, e.g., heat sinks (epo) |
587 |
| 257/E23.11 |
Cooling facilitated by selection of materials for device (or materials for thermal expansion adaptation, e.g., carbon) (epo) |
64 |
| 257/E23.113 |
Ceramic materials or glass (epo) |
87 |
| 257/E23.111 |
Diamond (epo) |
174 |
| 257/E23.112 |
Having heterogeneous or anisotropic structure, e.g., powder or fibers in matrix, wire mesh, porous structures (epo) |
285 |
| 257/E23.102 |
Cooling facilitated by shape of device (epo) |
329 |
| 257/E23.104 |
Characterized by shape of housing (epo) |
265 |
| 257/E23.103 |
Foil-like cooling fins or heat sinks (epo) |
462 |
| 257/E23.105 |
Wire-like or pin-like cooling fins or heat sinks (epo) |
495 |
| 257/E23.106 |
Laminates or multilayers, e.g., direct bond copper ceramic substrates (epo) |
361 |
| 257/E23.109 |
Metallic materials (epo) |
152 |
| 257/E23.107 |
Organic materials with or without thermo-conductive filler (epo) |
285 |
| 257/E23.108 |
Semiconductor materials (epo) |
29 |
| 257/E23.18 |
Containers; seals (epo) |
18 |
| 257/E23.191 |
Characterized by material of container or its electrical properties (epo) |
52 |
| 257/E23.192 |
Material being electrical insulator, e.g., glass (epo) |
73 |
| 257/E23.193 |
Characterized by material or arrangement of seals between parts, e.g., between cap and base of container or between leads and walls of container (epo) |
656 |
| 257/E23.181 |
Characterized by shape of container or parts, e.g., caps, walls (epo) |
312 |
| 257/E23.183 |
Container being hollow construction and having conductive base as mounting as well as lead for the semiconductor body (epo) |
18 |
| 257/E23.187 |
Another lead being formed by cover plate parallel to base plate, e.g., sandwich type (epo) |
211 |
| 257/E23.185 |
Other leads being parallel to base (epo) |
82 |
| 257/E23.186 |
Other leads being perpendicular to base (epo) |
62 |
| 257/E23.184 |
Other leads having insulating passage through base (epo) |
36 |
| 257/E23.188 |
Container being hollow construction and having insulating or insulated base as mounting for semiconductor body (epo) |
61 |
| 257/E23.189 |
Leads being parallel to base (epo) |
453 |
| 257/E23.19 |
Leads having passage through base (epo) |
191 |
| 257/E23.182 |
Container being hollow construction having no base used as mounting for semiconductor body (epo) |
27 |
| 257/E23.002 |
Details not otherwise provided for, e.g., protection against moisture (epo) |
254 |
| 257/E23.116 |
Encapsulations, e.g., encapsulating layers, coatings, e.g., for protection (epo) |
62 |
| 257/E23.123 |
Characterized by arrangement or shape (epo) |
44 |
| 257/E23.124 |
Device being completely enclosed (epo) |
1135 |
| 257/E23.126 |
Double encapsulation or coating and encapsulation (epo) |
287 |
| 257/E23.128 |
Encapsulation having cavity (epo) |
107 |
| 257/E23.127 |
Sealing arrangements between parts, e.g., adhesion promoters (epo) |
89 |
| 257/E23.125 |
Substrate forming part of encapsulation (epo) |
718 |
| 257/E23.129 |
Partial encapsulation or coating (epo) |
136 |
| 257/E23.133 |
Coating also covering sidewalls of semiconductor body (epo) |
73 |
| 257/E23.132 |
Coating being directly applied to semiconductor body, e.g., passivation layer (epo) |
381 |
| 257/E23.13 |
Coating being foil (epo) |
53 |
| 257/E23.131 |
Coating or filling in grooves made in semiconductor body (epo) |
50 |
| 257/E23.134 |
Multilayer coating (epo) |
129 |
| 257/E23.117 |
Characterized by material, e.g., carbon (epo) |
44 |
| 257/E23.119 |
Organic, e.g., plastic, epoxy (epo) |
588 |
| 257/E23.121 |
Containing filler (epo) |
180 |
| 257/E23.12 |
Organo-silicon compounds, e.g., silicone (epo) |
119 |
| 257/E23.118 |
Oxides or nitrides or carbides, e.g., ceramics, glass (epo) |
215 |
| 257/E23.122 |
Semiconductor material, e.g., amorphous silicon (epo) |
38 |
| 257/E23.135 |
Fillings or auxiliary members in containers or encapsulations, e.g., centering rings (epo) |
236 |
| 257/E23.136 |
Fillings characterized by material, its physical or chemical properties, or its arrangement within complete device (epo) |
17 |
| 257/E23.138 |
Gaseous at normal operating temperature of device (epo) |
17 |
| 257/E23.137 |
Including materials for absorbing or reacting with moisture or other undesired substances, e.g., getters (epo) |
79 |
| 257/E23.139 |
Liquid at normal operating temperature of device (epo) |
16 |
| 257/E23.14 |
Solid or gel at normal operating temperature of device (epo) |
395 |
| 257/E23.179 |
Marks applied to semiconductor devices or parts, e.g., registration marks, test patterns, alignment structures, wafer maps (epo) |
1198 |
| 257/E23.003 |
Mountings, e.g., nondetachable insulating substrates (epo) |
43 |
| 257/E23.005 |
Characterized by material or its electrical properties (epo) |
25 |
| 257/E23.009 |
Ceramic or glass substrates (epo) |
446 |
| 257/E23.006 |
Metallic substrates having insulating layers (epo) |
249 |
| 257/E23.007 |
Organic substrates, e.g., plastic (epo) |
237 |
| 257/E23.008 |
Semiconductor insulating substrates (epo) |
138 |
| 257/E23.004 |
Characterized by shape (epo) |
978 |
| 257/E23.194 |
Protection against mechanical damage (epo) |
212 |
| 257/E23.114 |
Protection against radiation, e.g., light, electromagnetic waves (epo) |
641 |
| 257/E23.115 |
Against alpha rays (epo) |
91 |
| 257/618 |
Physical configuration of semiconductor (e.g., mesa, bevel, groove, etc.) |
490 |
| 257/622 |
Groove |
635 |
| 257/623 |
Mesa structure (e.g., including undercut or stepped mesa configuration or having constant slope taper) |
408 |
| 257/626 |
Combined with passivating coating |
159 |
| 257/625 |
Semiconductor body including mesa is intimately bonded to thick electrical and/or thermal conductor member of larger lateral extent than semiconductor body (e.g., "plated heat sink" microwave diode) |
106 |
| 257/624 |
With low resistance ohmic connection means along exposed mesa edge (e.g., contact or heavily doped region along exposed mesa to reduce "skin effect" losses in microwave diode) |
75 |
| 257/621 |
With electrical contact in hole in semiconductor (e.g., lead extends through semiconductor body) |
280 |
| 257/620 |
With peripheral feature due to separation of smaller semiconductor chip from larger wafer (e.g., scribe region, or means to prevent edge effects such as leakage current at peripheral chip separation area) |
498 |
| 257/627 |
With specified crystal plane or axis |
362 |
| 257/628 |
Major crystal plane or axis other than (100), (110), or (111) (e.g., (731) axis, crystal plane several degrees from (100) toward (011), etc.) |
215 |
| 257/619 |
With thin active central semiconductor portion surrounded by thicker inactive shoulder (e.g., for mechanical support) |
133 |
| 257/658 |
Plate type rectifier array |
37 |
| 257/917 |
Plural dopants of same conductivity type in same region |
37 |
| 257/905 |
Plural dram cells share common contact or common trench |
125 |
| 257/929 |
Pn junction isolated integrated circuit with isolation walls having minimum dopant concentration at intermediate depth in epitaxial layer (e.g., diffused from both surfaces of epitaxial layer) |
21 |
| 257/41 |
Point contact device |
51 |
| 257/914 |
Polysilicon containing oxygen, nitrogen, or carbon (e.g., sipos) |
80 |
| 257/E21.001 |
Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) |
140 |
| 257/E21.532 |
Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) |
24 |
| 257/E21.705 |
Assembly of devices consisting of solid-state components formed in or on a common substrate; assembly of integrated circuit devices (epo) |
630 |
| 257/E21.536 |
Manufacture of specific parts of devices (epo) |
11 |
| 257/E21.575 |
Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) |
562 |
| 257/E21.576 |
Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) |
1965 |
| 257/E21.584 |
Barrier, adhesion or liner layer (epo) |
2372 |
| 257/E21.589 |
By forming conductive members before deposition of protective insulating material, e.g., pillars, studs (epo) |
571 |
| 257/E21.577 |
By forming via holes (epo) |
1894 |
| 257/E21.579 |
For "dual damascene" type structures (epo) |
1588 |
| 257/E21.578 |
Tapered via holes (epo) |
440 |
| 257/E21.582 |
Characterized by formation and post treatment of conductors, e.g., patterning (epo) |
1459 |
| 257/E21.581 |
Dielectric comprising air gaps (epo) |
460 |
| 257/E21.585 |
Filling of holes, grooves, vias or trenches with conductive material (epo) |
1668 |
| 257/E21.587 |
By deposition over sacrificial masking layer, e.g., lift-off (epo) |
137 |
| 257/E21.586 |
By selective deposition of conductive material in vias, e.g., selective chemical vapor deposition on semiconductor material, plating (epo) |
508 |
| 257/E21.588 |
Reflowing or applying pressure to fill contact hole, e.g., to remove voids (epo) |
223 |
| 257/E21.59 |
Local interconnects; local pads (epo) |
1005 |
| 257/E21.591 |
Modifying pattern or conductivity of conductive members, e.g., formation of alloys, reduction of contact resistances (epo) |
311 |
| 257/E21.592 |
By altering solid-state characteristics of conductive members, e.g., fuses, in situ oxidation, laser melting (epo) |
364 |
| 257/E21.593 |
By forming silicide of refractory metal (epo) |
287 |
| 257/E21.594 |
By using super-conducting material (epo) |
15 |
| 257/E21.595 |
Modifying pattern (epo) |
100 |
| 257/E21.596 |
Using laser, e.g., laser cutting, laser direct writing, laser repair (epo) |
196 |
| 257/E21.583 |
Planarization; smoothing (epo) |
743 |
| 257/E21.58 |
Planarizing dielectric (epo) |
562 |
| 257/E21.597 |
Formed through semiconductor substrate (epo) |
387 |
| 257/E21.54 |
Making of isolation regions between components (epo) |
163 |
| 257/E21.573 |
Air gaps (epo) |
266 |
| 257/E21.543 |
Between components manufactured in active substrate comprising group ii-vi compound semiconductor (epo) |
0 |
| 257/E21.542 |
Between components manufactured in active substrate comprising group iii-v compound semiconductor (epo) |
117 |
| 257/E21.541 |
Between components manufactured in active substrate comprising sic compound semiconductor (epo) |
23 |
| 257/E21.545 |
Dielectric regions, e.g., epic dielectric isolation, locos; trench refilling techniques, soi technology, use of channel stoppers (epo) |
302 |
| 257/E21.56 |
Dielectric isolation using epic technique, i.e., epitaxial passivated integrated circuit (epo) |
171 |
| 257/E21.552 |
Using local oxidation of silicon, e.g., locos, swami, silo (epo) |
539 |
| 257/E21.553 |
In region recessed from surface, e.g., in recess, groove, tub or trench region (epo) |
186 |
| 257/E21.555 |
Recessed region having shape other than rectangular, e.g., rounded or oblique shape (epo) |
88 |
| 257/E21.554 |
Using auxiliary pillars in recessed region, e.g., to form locos over extended areas (epo) |
42 |
| 257/E21.556 |
Introducing electrical inactive or active impurities in local oxidation region, e.g., to alter locos oxide growth characteristics or for additional isolation purpose (epo) |
114 |
| 257/E21.557 |
Introducing electrical active impurities in local oxidation region solely for forming channel stoppers (epo) |
229 |
| 257/E21.558 |
Introducing both types of electrical active impurities in local oxidation region solely for forming channel stoppers, e.g., for isolation of complementary doped regions (epo) |
103 |
| 257/E21.559 |
With plurality of successive local oxidation steps (epo) |
86 |
| 257/E21.571 |
Using selective deposition of single crystal silicon, i.e., seg technique (epo) |
86 |
| 257/E21.561 |
Using semiconductor or insulator technology, i.e., soi technology (epo) |
247 |
| 257/E21.564 |
Soi together with lateral isolation, e.g., using local oxidation of silicon, or dielectric or polycrystalline material refilled trench or air gap isolation regions, e.g., completely isolated semiconductor islands (epo) |
791 |
| 257/E21.567 |
Using bonding technique (epo) |
406 |
| 257/E21.569 |
Using silicon etch back technique, e.g., besoi, eltran (epo) |
114 |
| 257/E21.568 |
With separation/delamination along ion implanted layer, e.g., "smart-cut", "unibond" (epo) |
313 |
| 257/E21.57 |
With separation/delamination along porous layer (epo) |
145 |
| 257/E21.565 |
Using full isolation by porous oxide silicon, i.e., fipos technique (epo) |
28 |
| 257/E21.566 |
Using lateral overgrowth technique, i.e., elo techniques (epo) |
57 |
| 257/E21.562 |
Using selective deposition of single crystal silicon, e.g., selective epitaxial growth (seg) (epo) |
56 |
| 257/E21.563 |
Using silicon implanted buried insulating layers, e.g., oxide layers, i.e., simox technique (epo) |
176 |
| 257/E21.546 |
Using trench refilling with dielectric materials (epo) |
1152 |
| 257/E21.548 |
Concurrent filling of plurality of trenches having different trench shape or dimension, e.g., rectangular and v-shaped trenches, wide and narrow trenches, shallow and deep trenches (epo) |
634 |
| 257/E21.547 |
Dielectric material being obtained by full chemical transformation of nondielectric materials, such as polycrystalline silicon, metals (epo) |
89 |
| 257/E21.551 |
Introducing impurities in trench side or bottom walls, e.g., for forming channel stoppers or alter isolation behavior (epo) |
334 |
| 257/E21.549 |
Of trenches having shape other than rectangular or v shape, e.g., rounded corners, oblique or rounded trench walls (epo) |
543 |
| 257/E21.55 |
Trench shape altered by local oxidation of silicon process step, e.g., trench corner rounding by locos (epo) |
210 |
| 257/E21.574 |
Isolation by field effect (epo) |
133 |
| 257/E21.544 |
Pn junction isolation (epo) |
487 |
| 257/E21.572 |
Polycrystalline semiconductor regions (epo) |
500 |
| 257/E21.537 |
Making of localized buried regions, e.g., buried collector layer, internal connection, substrate contacts (epo) |
321 |
| 257/E21.539 |
For group iii-v compound semiconductor integrated circuits (epo) |
6 |
| 257/E21.538 |
Making of internal connections, substrate contacts (epo) |
410 |
| 257/E21.598 |
Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) |
22 |
| 257/E21.599 |
With subsequent division of substrate into plural individual devices (epo) |
562 |
| 257/E21.6 |
Involving separation of active layers from substrate (epo) |
25 |
| 257/E21.601 |
Leaving reusable substrate, e.g., epitaxial lift-off process (epo) |
8 |
| 257/E21.7 |
Substrate is nonsemiconductor body, e.g., insulating body (epo) |
15 |
| 257/E21.701 |
Substrate is sapphire, e.g., silicon on sapphire structure (sos) (epo) |
2 |
| 257/E21.703 |
Substrate is semiconductor body (epo) |
2635 |
| 257/E21.704 |
Substrate is nonsemiconductor body, e.g., insulating body (epo) |
148 |
| 257/E21.702 |
To produce devices, each consisting of single circuit element (epo) |
2 |
| 257/E21.602 |
To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) |
118 |
| 257/E21.606 |
Substrate being semiconductor, using silicon technology (epo) |
49 |
| 257/E21.608 |
Bipolar technology (epo) |
173 |
| 257/E21.611 |
Complementary devices, e.g., complementary transistors (epo) |
32 |
| 257/E21.612 |
Complementary vertical transistors (epo) |
96 |
| 257/E21.609 |
Comprising combination of vertical and lateral transistors (epo) |
41 |
| 257/E21.61 |
Comprising merged transistor logic or integrated injection logic (epo) |
59 |
| 257/E21.613 |
Memory structures (epo) |
63 |
| 257/E21.695 |
Combination of bipolar and field-effect technologies (epo) |
50 |
| 257/E21.696 |
Bipolar and mos technologies (epo) |
758 |
| 257/E21.615 |
Field-effect technology (epo) |
11 |
| 257/E21.616 |
Mis technology (epo) |
122 |
| 257/E21.617 |
Combination of charge coupled devices, i.e., ccd or bbd (epo) |
74 |
| 257/E21.631 |
Combination of enhancement and depletion transistors (epo) |
43 |
| 257/E21.632 |
Complementary field-effect transistors, e.g., cmos (epo) |
427 |
| 257/E21.641 |
Interconnection or wiring or contact manufacturing related aspects (epo) |
187 |
| 257/E21.642 |
Isolation region manufacturing related aspects, e.g., to avoid interaction of isolation region with adjacent structure (epo) |
319 |
| 257/E21.633 |
With particular manufacturing method of channel, e.g., channel implants, halo or pocket implants, or channel materials (epo) |
506 |
| 257/E21.635 |
With particular manufacturing method of gate conductor, e.g., particular materials, shapes (epo) |
128 |
| 257/E21.637 |
Gate conductors with different gate conductor materials or different gate conductor implants, e.g., dual gate structures (epo) |
424 |
| 257/E21.638 |
Gate conductors with different shapes, lengths or dimensions (epo) |
92 |
| 257/E21.636 |
Silicided or salicided gate conductors (epo) |
233 |
| 257/E21.639 |
With particular manufacturing method of gate insulating layer, e.g., different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants (epo) |
271 |
| 257/E21.64 |
With particular manufacturing method of gate sidewall spacers, e.g., double spacers, particular spacer material or shape (epo) |
262 |
| 257/E21.634 |
With particular manufacturing method of source or drain, e.g., specific s or d implants or silicided s or d structures or raised s or d structures (epo) |
571 |
| 257/E21.643 |
With particular manufacturing method of vertical transistor structures, i.e., with channel vertical to substrate surface (epo) |
64 |
| 257/E21.646 |
Dynamic random access memory structures (dram) (epo) |
376 |
| 257/E21.647 |
Characterized by type of capacitor (epo) |
310 |
| 257/E21.648 |
Capacitor stacked over transfer transis tor (epo) |
1913 |
| 257/E21.65 |
Capacitor extending under transfer transistor area (epo) |
56 |
| 257/E21.651 |
Capacitor in u- or v-shaped trench in substrate (epo) |
458 |
| 257/E21.652 |
In combination with vertical transistor (epo) |
287 |
| 257/E21.653 |
Making connection between transistor and capacitor, e.g., buried strap (epo) |
183 |
| 257/E21.649 |
Making connection between transistor and capacitor, e.g., plug (epo) |
504 |
| 257/E21.656 |
Characterized by data lines (epo) |
120 |
| 257/E21.657 |
Making bit line (epo) |
315 |
| 257/E21.658 |
Making bit line contact (epo) |
453 |
| 257/E21.659 |
Making word line (epo) |
169 |
| 257/E21.654 |
Characterized by type of transistor; manufacturing of transistor (epo) |
650 |
| 257/E21.655 |
Transistor in u- or v-shaped trench in substrate (epo) |
257 |
| 257/E21.66 |
Simultaneous fabrication of periphery and memory cells (epo) |
781 |
| 257/E21.662 |
Read-only memory structures (rom), i.e., nonvolatile memory structures (epo) |
88 |
| 257/E21.679 |
Charge trapping insulator nonvolatile memory structures (epo) |
462 |
| 257/E21.68 |
Electrically programmable (eprom), i.e., floating gate memory structures (epo) |
365 |
| 257/E21.681 |
With conductive layer as control gate (epo) |
23 |
| 257/E21.682 |
With source and drain on same level and without cell select transistor (epo) |
1487 |
| 257/E21.683 |
Simultaneous fabrication of periphery and memory cells (epo) |
85 |
| 257/E21.684 |
Including one type of peripheral fet (epo) |
60 |
| 257/E21.685 |
Control gate layer used for peripheral fet (epo) |
95 |
| 257/E21.686 |
Intergate dielectric layer used for peripheral fet (epo) |
35 |
| 257/E21.687 |
Floating gate layer used for peripheral fet (epo) |
43 |
| 257/E21.688 |
Floating gate dielectric layer used for peripheral fet (epo) |
152 |
| 257/E21.689 |
Including different types of peripheral fets (epo) |
373 |
| 257/E21.69 |
With source and drain on same level and with cell select transistor (epo) |
247 |
| 257/E21.691 |
Simultaneous fabrication of periphery and memory cells (epo) |
94 |
| 257/E21.692 |
With source and drain on different levels, e.g., sloping channel (epo) |
36 |
| 257/E21.693 |
For vertical channel (epo) |
126 |
| 257/E21.694 |
With doped region as control gate (epo) |
89 |
| 257/E21.663 |
Ferroelectric nonvolatile memory structures (epo) |
78 |
| 257/E21.664 |
With ferroelectric capacitor (epo) |
444 |
| 257/E21.665 |
Magnetic nonvolatile memory structures, e.g., mram (epo) |
324 |
| 257/E21.666 |
Prom (epo) |
31 |
| 257/E21.667 |
Rom only (epo) |
13 |
| 257/E21.678 |
Simultaneous fabrication of periphery and memory cells (epo) |
34 |
| 257/E21.677 |
With fets on different levels, e.g., 3d rom (epo) |
15 |
| 257/E21.676 |
With source and drain on different levels, e.g., vertical channel (epo) |
43 |
| 257/E21.668 |
With source and drain on same level, e.g., lateral channel (epo) |
28 |
| 257/E21.671 |
Doping programmed, e.g., mask rom (epo) |
60 |
| 257/E21.672 |
Entire channel doping programmed (epo) |
208 |
| 257/E21.673 |
Source or drain doping programmed (epo) |
67 |
| 257/E21.67 |
Gate contact programmed (epo) |
16 |
| 257/E21.675 |
Gate dielectric programmed, e.g., different thickness (epo) |
33 |
| 257/E21.674 |
Gate programmed, e.g., different gate material or no gate (epo) |
16 |
| 257/E21.669 |
Source or drain contact programmed (epo) |
32 |
| 257/E21.661 |
Static random access memory structures (sram) (epo) |
794 |
| 257/E21.627 |
Interconnection or wiring or contact manufacturing related aspects (epo) |
174 |
| 257/E21.628 |
Isolation region manufacturing related aspects, e.g., to avoid interaction of isolation region with adjacent structure (epo) |
327 |
| 257/E21.645 |
Memory structures (epo) |
316 |
| 257/E21.618 |
With particular manufacturing method of channel, e.g., channel implants, halo or pocket implants, or channel materials (epo) |
191 |
| 257/E21.621 |
With particular manufacturing method of gate conductor, e.g., particular materials, shapes (epo) |
128 |
| 257/E21.623 |
Gate conductors with different gate conductor materials or different gate conductor implants, e.g., dual gate structures (epo) |
141 |
| 257/E21.624 |
Gate conductors with different shapes, lengths or dimensions (epo) |
115 |
| 257/E21.622 |
Silicided or salicided gate conductors (epo) |
119 |
| 257/E21.625 |
With particular manufacturing method of gate insulating layer, e.g., different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants (epo) |
429 |
| 257/E21.626 |
With particular manufacturing method of gate sidewall spacers, e.g., double spacers, particular spacer material or shape (epo) |
244 |
| 257/E21.619 |
With particular manufacturing method of source or drain, e.g., specific s or d implants or silicided s or d structures or raised s or d structures (epo) |
242 |
| 257/E21.62 |
Manufacturing common source or drain regions between plurality of conductor-insulator-semiconductor structures (epo) |
193 |
| 257/E21.629 |
With particular manufacturing method of vertical transistor structures, i.e., with channel vertical to substrate surface (epo) |
120 |
| 257/E21.63 |
With particular manufacturing method of wells or tubs, e.g., twin tubs, high energy well implants, buried implanted layers for lateral isolation (billi) (epo) |
90 |
| 257/E21.644 |
With particular manufacturing method of wells or tubs, e.g., twin tubs, high energy well implants, buried implanted layers for lateral isolation (billi) (epo) |
317 |
| 257/E21.614 |
Three-dimensional integrated circuits stacked in different levels (epo) |
319 |
| 257/E21.698 |
Substrate is group ii-vi semiconductor (epo) |
9 |
| 257/E21.697 |
Substrate is group iii-v semiconductor (epo) |
206 |
| 257/E21.699 |
Substrate is semiconductor other than diamond, sic, si, group iii-v compound, or group ii-vi compound (epo) |
13 |
| 257/E21.603 |
Substrate is semiconductor, using combination of semiconductor substrates, e.g., diamond, sic, si, group iii-v compound, and/or group ii-vi compound semiconductor substrates (epo) |
41 |
| 257/E21.604 |
Substrate is semiconductor, using diamond technology (epo) |
1 |
| 257/E21.605 |
Substrate is semiconductor, using sic technology (epo) |
27 |
| 257/E21.533 |
Of thick- or thin-film circuits or parts thereof (epo) |
32 |
| 257/E21.534 |
Of thick-film circuits or parts thereof (epo) |
47 |
| 257/E21.535 |
Of thin-film circuits or parts thereof (epo) |
48 |
| 257/E21.002 |
Manufacture or treatment of semiconductor device (epo) |
104 |
| 257/E21.04 |
Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) |
20 |
| 257/E21.499 |
Assembling semiconductor devices, e.g., packaging , including mounting, encapsulating, or treatment of packaged semiconductor (epo) |
576 |
| 257/E21.506 |
Attaching or detaching leads or other conductive members, to be used for carrying current to or from device in operation (epo) |
80 |
| 257/E21.507 |
Formation of contacts to semiconductor by use of metal layers separated by insulating layers, e.g., self-aligned contacts to source/drain or emitter/base (epo) |
1406 |
| 257/E21.508 |
Forming solder bumps (epo) |
1672 |
| 257/E21.518 |
Involving application of mechanical vibration, e.g., ultrasonic vibration (epo) |
389 |
| 257/E21.519 |
Involving application of pressure, e.g., thermo-compression bonding (epo) |
291 |
| 257/E21.516 |
Involving automation techniques using film carriers (epo) |
223 |
| 257/E21.509 |
Involving soldering or alloying process, e.g., soldering wires (epo) |
213 |
| 257/E21.511 |
Mounting on insulating member provided with metallic leads, e.g., flip-chip mounting, conductive die mounting (epo) |
1472 |
| 257/E21.512 |
Right-up bonding (epo) |
518 |
| 257/E21.51 |
Mounting on metallic conductive member (epo) |
175 |
| 257/E21.513 |
Mounting on semiconductor conductive member (epo) |
32 |
| 257/E21.514 |
Involving use of conductive adhesive (epo) |
433 |
| 257/E21.517 |
Involving use of electron or laser beam (epo) |
61 |
| 257/E21.515 |
Involving use of mechanical auxiliary part without use of alloying or soldering process, e.g., pressure contacts (epo) |
19 |
| 257/E21.502 |
Encapsulation, e.g., encapsulation layer, coating (epo) |
709 |
| 257/E21.503 |
Encapsulation of active face of flip chip device, e.g., under filling or under encapsulation of flip-chip, encapsulation perform on chip or mounting substrate (epo) |
1359 |
| 257/E21.504 |
Moulds (epo) |
1008 |
| 257/E21.505 |
Insulative mounting semiconductor device on support (epo) |
678 |
| 257/E21.5 |
Mounting semiconductor bodies in container (epo) |
60 |
| 257/E21.501 |
Providing fillings in container, e.g., gas fillings (epo) |
23 |
| 257/E21.041 |
Device having semiconductor body comprising carbon, e.g., diamond, diamond-like carbon (epo) |
26 |
| 257/E21.044 |
Changing their shape, e.g., forming recess (epo) |
7 |
| 257/E21.045 |
Making electrode (epo) |
3 |
| 257/E21.048 |
Conductor-insulator-semiconductor electrode, e.g., mis contacts (epo) |
9 |
| 257/E21.046 |
Ohmic electrode (epo) |
20 |
| 257/E21.047 |
Schottky electrode (epo) |
17 |
| 257/E21.042 |
Making n- or p-doped regions (epo) |
11 |
| 257/E21.043 |
Using ion im plantation (epo) |
31 |
| 257/E21.049 |
Multistep processes for manufacture of device whose active layer, e.g., base, channel, comprises semiconducting carbon, e.g., diamond, diamond-like carbon (epo) |
8 |
| 257/E21.05 |
Device controllable only by electric current supplied or the electric potential applied to electrode which does not carry current to be rectified, amplified, or switched, e.g., three-terminal devices such as source, drain, and gate terminals; emitter, base, collector terminals (epo) |
10 |
| 257/E21.051 |
Field-effect transistor (epo) |
68 |
| 257/E21.052 |
Device controllable only by variation of electric current supplied or the electric potential applied to electrodes carrying current to be rectified, amplified, oscillated, or switched, e.g., two-terminal device (epo) |
3 |
| 257/E21.053 |
Diode (epo) |
28 |
| 257/E21.078 |
Device having semiconductor body comprising cuprous oxide (cu 2 o) or cuprous iodide (cui) (epo) |
3 |
| 257/E21.079 |
Preparation of substrate, preliminary treatment oxidation of substrate, reduction treatment (epo) |
7 |
| 257/E21.083 |
Application of specified conductive layer (epo) |
0 |
| 257/E21.082 |
Oxidation and subsequent heat treatment of substrate (epo) |
10 |
| 257/E21.08 |
Preliminary treatment of foundation plate (epo) |
3 |
| 257/E21.081 |
Reduction of copper oxide, treatment of oxide layer (epo) |
3 |
| 257/E21.084 |
Treatment of complete device, e.g., electroforming, heat treating (epo) |
5 |
| 257/E21.085 |
Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) |
20 |
| 257/E21.154 |
Alloying of impurity material, e.g., doping material, electrode material, with a semiconductor body (epo) |
108 |
| 257/E21.155 |
Alloying of doping material with group iii-v compound (epo) |
10 |
| 257/E21.156 |
Alloying of electrode material (epo) |
7 |
| 257/E21.157 |
With group iii-v compound (epo) |
6 |
| 257/E21.09 |
Deposition of semiconductor material on substrate, e.g., epitaxial growth, solid phase epitaxy (epo) |
180 |
| 257/E21.119 |
Characterized by the substrate (epo) |
134 |
| 257/E21.122 |
Bonding of semiconductor wafer to insulating substrate or to semic onducting substrate using an intermediate insulating layer (epo) |
462 |
| 257/E21.123 |
Substrate is crystalline semiconductor material, e.g., lattice adaptation, heteroepitaxy (epo) |
144 |
| 257/E21.128 |
Carbon on a noncarbon semiconductor substrate (epo) |
16 |
| 257/E21.125 |
Defect and dislocati on suppression due to lattice mismatch, e.g., lattice adaptation (epo) |
304 |
| 257/E21.126 |
Group iii-v compound on dissimilar group iii-v compound (epo) |
98 |
| 257/E21.127 |
Group iii-v compound on si or ge (epo) |
207 |
| 257/E21.124 |
Heteroepitaxy (epo) |
16 |
| 257/E21.12 |
Characterized by the post-treatment used to control the interface betw een substrate and epitaxial layer, e.g., ion implantation followed by annealing (epo) |
73 |
| 257/E21.129 |
Group iva, e.g., si, c, ge on group ivb, e.g., ti, zr (epo) |
109 |
| 257/E21.121 |
Substrate is crystalline insulating material, e.g., sapphire (epo) |
215 |
| 257/E21.13 |
The substrate is crystalline conducting material, e.g., metallic silicide (epo) |
34 |
| 257/E21.133 |
Epitaxial re-growth of non-monocrystalline semiconductor material, e.g., lateral epitaxy by seeded solidific ation, solid-state crystallization, solid-state graphoepitaxy, explosive crystallization, grain growth in polycrystalline material (epo) |
721 |
| 257/E21.134 |
Using a coherent energy beam, e.g., laser or electron beam (epo) |
628 |
| 257/E21.131 |
Selective epilaxial growth, e.g., simultaneous deposition of mono- and non-mono semiconductor material (epo) |
621 |
| 257/E21.132 |
Preparation of substrate for selective epitaxy (epo) |
30 |
| 257/E21.114 |
Using liquid deposition (epo) |
51 |
| 257/E21.117 |
Epitaxial deposition of group iii-v compound (epo) |
118 |
| 257/E21.118 |
Deposition on a semiconductor substrate not being an group iii-v compound (epo) |
5 |
| 257/E21.115 |
Epitaxial deposition of group iv elements, e.g., si, ge, c (epo) |
30 |
| 257/E21.116 |
Deposition on a semiconductor substrate which is different from the semiconductor material being deposited, i.e., formation of heterojunction (epo) |
4 |
| 257/E21.091 |
Using physical deposition, e.g., vacuum deposition, sputtering (epo) |
67 |
| 257/E21.096 |
Deposition of diamond (epo) |
1 |
| 257/E21.097 |
Epitaxial deposition of group iii-v compound (epo) |
114 |
| 257/E21.099 |
Deposition on insulating or metallic substrate (epo) |
13 |
| 257/E21.098 |
Deposition on semiconductor substrate not being an group iii-v compound (epo) |
15 |
| 257/E21.1 |
Doping during epitaxial deposition (epo) |
24 |
| 257/E21.092 |
Epitaxial deposition of group iv element, e.g., si, ge (epo) |
70 |
| 257/E21.094 |
Deposition on insulating or meta llic substrate (epo) |
28 |
| 257/E21.093 |
Deposition on semiconductor substrate being different from deposited semiconductor material; i.e., formation of heterojunctions (epo) |
15 |
| 257/E21.095 |
Epitaxial deposition of diamond (epo) |
2 |
| 257/E21.101 |
Using reduction or decomposition of gaseous compound yielding solid condensate, i.e., chemical deposition (epo) |
499 |
| 257/E21.107 |
Deposition of diamond (epo) |
6 |
| 257/E21.108 |
Epitaxial deposition of group iii-v compound (epo) |
215 |
| 257/E21.112 |
Deposition on a semiconductor substrate not being group iii-v compound (epo) |
110 |
| 257/E21.113 |
Deposition on an insulating or a metallic substrate (epo) |
82 |
| 257/E21.11 |
Doping the epitaxial deposit (epo) |
85 |
| 257/E21.111 |
Doping with transition metals to form semi-insulating layers (epo) |
26 |
| 257/E21.109 |
Using molecular beam technique (epo) |
17 |
| 257/E21.102 |
Epitaxial deposition of group iv elements, e.g., si, ge, c (epo) |
173 |
| 257/E21.103 |
Deposition on a semiconductor substrate which is different from the semiconductor material being deposited, i.e., formation of heterojunctions (epo) |
31 |
| 257/E21.104 |
Deposition on an insulating or a metallic substrate (epo) |
36 |
| 257/E21.106 |
Doping during the epitaxial deposition (epo) |
53 |
| 257/E21.105 |
Epitaxial deposition of diamond (epo) |
11 |
| 257/E21.135 |
Diffusion of impurity material, e.g., doping material, electrode material, into or out of a semiconductor body, or between semiconductor regions; interactions between two or more impurities; redistribution of impurities (epo) |
106 |
| 257/E21.14 |
Diffusion source (epo) |
64 |
| 257/E21.136 |
From the substrate during epitaxy, e.g., autodoping; preventing or using autodoping (epo) |
62 |
| 257/E21.139 |
Lithium-drift (epo) |
3 |
| 257/E21.137 |
To control carrier lifetime, i.e., deep level dopant (epo) |
39 |
| 257/E21.138 |
In group iii-v compound (epo) |
5 |
| 257/E21.144 |
Using diffusion into or out of a s olid from or into a solid phase, e.g., a doped oxide layer (epo) |
24 |
| 257/E21.152 |
Diffusion into or out of group iii-v compound (epo) |
60 |
| 257/E21.145 |
Diffusion into or out of group iv semiconductor (epo) |
18 |
| 257/E21.148 |
From or through or into an applied layer, e.g., photoresist, nitride (epo) |
130 |
| 257/E21.151 |
Applied layer being silicon or silicide or sipos, e.g., polysilicon, porous silicon (epo) |
