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Class Information
Number: 148/DIG.85
Name: Metal treatment > Isolated-integrated
Description:










Patents under this class:
1 2 3 4

Patent Number Title Of Patent Date Issued
5981326 Damascene isolation of CMOS transistors Nov. 9, 1999
5899714 Fabrication of semiconductor structure having two levels of buried regions May. 4, 1999
5795801 MethodS of fabricating profiled device wells for improved device isolation Aug. 18, 1998
5770504 Method for increasing latch-up immunity in CMOS devices Jun. 23, 1998
5536665 Method of manufacturing a semiconductor device with double structured well Jul. 16, 1996
5496760 Method for manufacturing dielectrics dividing wafer with isolated regions Mar. 5, 1996
5416039 Method of making BiCDMOS structures May. 16, 1995
5344785 Method of forming high speed, high voltage fully isolated bipolar transistors on a SOI substrate Sep. 6, 1994
5294559 Method of forming a vertical transistor Mar. 15, 1994
5156989 Complementary, isolated DMOS IC technology Oct. 20, 1992
5132235 Method for fabricating a high voltage MOS transistor Jul. 21, 1992
5091336 Method of making a high breakdown active device structure with low series resistance Feb. 25, 1992
5082793 Method for making solid state device utilizing ion implantation techniques Jan. 21, 1992
5064771 Method of forming crystal array Nov. 12, 1991
4946800 Method for making solid-state device utilizing isolation grooves Aug. 7, 1990
4874718 Method for forming SOI film Oct. 17, 1989
4784970 Process for making a double wafer moated signal processor Nov. 15, 1988
4682408 Method for making field oxide region with self-aligned channel stop implantation Jul. 28, 1987
4680614 Planar void free isolation structure Jul. 14, 1987
4677456 Semiconductor structure and manufacturing method Jun. 30, 1987
4649630 Process for dielectrically isolated semiconductor structure Mar. 17, 1987
4642880 Method for manufacturing a recessed semiconductor device Feb. 17, 1987
4641416 Method of making an integrated circuit structure with self-aligned oxidation to isolate extrinsic base from emitter Feb. 10, 1987
4637128 Method of producing semiconductor device Jan. 20, 1987
4636269 Epitaxially isolated semiconductor device process utilizing etch and refill technique Jan. 13, 1987
4635090 Tapered groove IC isolation Jan. 6, 1987
4631803 Method of fabricating defect free trench isolation devices Dec. 30, 1986
4631804 Technique for reducing substrate warpage springback using a polysilicon subsurface strained layer Dec. 30, 1986
4631570 Integrated circuit having buried oxide isolation and low resistivity substrate for power supply interconnection Dec. 23, 1986
4628591 Method for obtaining full oxide isolation of epitaxial islands in silicon utilizing selective oxidation of porous silicon Dec. 16, 1986
4628341 Integrated circuit structure comprising CMOS transistors having high blocking voltage capability and method of fabrication of said structure Dec. 9, 1986
4624047 Fabrication process for a dielectric isolated complementary integrated circuit Nov. 25, 1986
4615104 Method of forming isolation regions containing conductive patterns therein Oct. 7, 1986
4615103 Method of forming isolation regions containing conductive patterns therein Oct. 7, 1986
4612072 Method for growing low defect, high purity crystalline layers utilizing lateral overgrowth of a patterned mask Sep. 16, 1986
4609413 Method for manufacturing and epitaxially isolated semiconductor utilizing etch and refill technique Sep. 2, 1986
4593459 Monolithic integrated circuit structure and method of fabrication Jun. 10, 1986
4589193 Metal silicide channel stoppers for integrated circuits and method for making the same May. 20, 1986
4583282 Process for self-aligned buried layer, field guard, and isolation Apr. 22, 1986
4581814 Process for fabricating dielectrically isolated devices utilizing heating of the polycrystalline support layer to prevent substrate deformation Apr. 15, 1986
4577394 Reduction of field oxide encroachment in MOS fabrication Mar. 25, 1986
4573257 Method of forming self-aligned implanted channel-stop and buried layer utilizing non-single crystal alignment key Mar. 4, 1986
4571818 Isolation process for high-voltage semiconductor devices Feb. 25, 1986
4570330 Method of producing isolated regions for an integrated circuit substrate Feb. 18, 1986
4567646 Method for fabricating a dielectric isolated integrated circuit device Feb. 4, 1986
4561172 Integrated circuit fabrication method utilizing selective etching and oxidation to form isolation regions Dec. 31, 1985
4546538 Method of manufacturing semiconductor integrated circuit devices having dielectric isolation regions Oct. 15, 1985
4546539 I.sup.2 L Structure and fabrication process compatible with high voltage bipolar transistors Oct. 15, 1985
4546537 Method for producing a semiconductor device utilizing V-groove etching and thermal oxidation Oct. 15, 1985
4542579 Method for forming aluminum oxide dielectric isolation in integrated circuits Sep. 24, 1985

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