| Patent Number |
Title Of Patent |
Date Issued |
| 6150220 |
Insulation layer structure and method for making the same |
Nov. 21, 2000 |
| 6124153 |
Method for manufacturing a polysilicon TFT with a variable thickness gate oxide |
Sep. 26, 2000 |
| 5650344 |
Method of making non-uniformly nitrided gate oxide |
Jul. 22, 1997 |
| 5610082 |
Method for fabricating thin film transistor using back light exposure |
Mar. 11, 1997 |
| 5593921 |
Method of forming vias |
Jan. 14, 1997 |
| 5488015 |
Method of making an interconnect structure with an integrated low density dielectric |
Jan. 30, 1996 |
| 5474956 |
Method of fabricating metallized substrates using an organic etch block layer |
Dec. 12, 1995 |
| 5397725 |
Method of controlling oxide thinning in an EPROM or flash memory array |
Mar. 14, 1995 |
| 5371047 |
Chip interconnection having a breathable etch stop layer |
Dec. 6, 1994 |
| 5294295 |
Method for moisture sealing integrated circuits using silicon nitride spacer protection of oxide passivation edges |
Mar. 15, 1994 |
| 5286677 |
Method for etching improved contact openings to peripheral circuit regions of a dram integrated circuit |
Feb. 15, 1994 |
| 5219792 |
Method for forming multilevel interconnection in a semiconductor device |
Jun. 15, 1993 |
| 5210045 |
Dual dielectric field effect transistors for protected gate structures for improved yield and performance in thin film transistor matrix addressed liquid crystal displays |
May. 11, 1993 |
| 5208189 |
Process for plugging defects in a dielectric layer of a semiconductor device |
May. 4, 1993 |
| 5196358 |
Method of manufacturing InP junction FETS and junction HEMTS using dual implantation and double nitride layers |
Mar. 23, 1993 |
| 5182221 |
Method of filling a recess flat with a material by a bias ECR-CVD process |
Jan. 26, 1993 |
| 5171705 |
Self-aligned structure and process for DMOS transistor |
Dec. 15, 1992 |
| 5094984 |
Suppression of water vapor absorption in glass encapsulation |
Mar. 10, 1992 |
| 5073510 |
Fabrication method of contact window in semiconductor device |
Dec. 17, 1991 |
| 5070037 |
Integrated circuit interconnect having dual dielectric intermediate layer |
Dec. 3, 1991 |
| 5061644 |
Method for fabricating self-aligned semiconductor devices |
Oct. 29, 1991 |
| 5023192 |
Method of manufacturing a bipolar transistor |
Jun. 11, 1991 |
| 5006485 |
Method of manufacturing an intergrated circuit including steps for forming interconnections between patterns formed at different levels |
Apr. 9, 1991 |
| 5003062 |
Semiconductor planarization process for submicron devices |
Mar. 26, 1991 |
| 5001076 |
Process for fabricating III-V devices using a composite dielectric layer |
Mar. 19, 1991 |
| 4996165 |
Self-aligned dielectric assisted planarization process |
Feb. 26, 1991 |
| 4966865 |
Method for planarization of a semiconductor device prior to metallization |
Oct. 30, 1990 |
| 4960723 |
Process for making a self aligned vertical field effect transistor having an improved source contact |
Oct. 2, 1990 |
| 4870032 |
Method of fabricating single crystal films of cubic group II fluorides on semiconductor componds by molecular beam epitaxy |
Sep. 26, 1989 |
| 4845048 |
Method of fabricating semiconductor device |
Jul. 4, 1989 |
| 4828629 |
Process of fabricating silicon oxide and gettering films on polycrystalline silicon resistance element |
May. 9, 1989 |
| 4808552 |
Process for making vertically-oriented interconnections for VLSI devices |
Feb. 28, 1989 |
| 4795722 |
Method for planarization of a semiconductor device prior to metallization |
Jan. 3, 1989 |
| 4692997 |
Method for fabricating MOMOM tunnel emission transistor |
Sep. 15, 1987 |
| 4692998 |
Process for fabricating semiconductor components |
Sep. 15, 1987 |
| 4665608 |
Method of manufacturing semiconductor devices |
May. 19, 1987 |
| 4649630 |
Process for dielectrically isolated semiconductor structure |
Mar. 17, 1987 |
| 4641420 |
Metalization process for headless contact using deposited smoothing material |
Feb. 10, 1987 |
| 4621277 |
Semiconductor device having insulating film |
Nov. 4, 1986 |
| 4581622 |
UV erasable EPROM with UV transparent silicon oxynitride coating |
Apr. 8, 1986 |
| 4571819 |
Method for forming trench isolation structures |
Feb. 25, 1986 |
| 4558508 |
Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step |
Dec. 17, 1985 |
| 4536947 |
CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors |
Aug. 27, 1985 |
| 4469568 |
Method for making thin-film transistors |
Sep. 4, 1984 |
| 4333964 |
Method of making integrated circuits |
Jun. 8, 1982 |
| 4282543 |
Semiconductor substrate and method for the preparation of the same |
Aug. 4, 1981 |
| 4199384 |
Method of making a planar semiconductor on insulating substrate device utilizing the deposition of a dual dielectric layer between device islands |
Apr. 22, 1980 |
| 4192059 |
Process for and structure of high density VLSI circuits, having inherently self-aligned gates and contacts for FET devices and conducting lines |
Mar. 11, 1980 |
| 4144634 |
Fabrication of gallium arsenide MOS devices |
Mar. 20, 1979 |
| 4110125 |
Method for fabricating semiconductor devices |
Aug. 29, 1978 |
