| Patent Number |
Title Of Patent |
Date Issued |
| 7195950 |
Forming a plurality of thin-film devices |
Mar. 27, 2007 |
| 5801089 |
Method of forming stacked devices |
Sep. 1, 1998 |
| 5691239 |
Method for fabricating an electrical connect above an integrated circuit |
Nov. 25, 1997 |
| 5668046 |
Method of producing a semiconductor on insulating substrate, and a method of forming transistor thereon |
Sep. 16, 1997 |
| 5656548 |
Method for forming three dimensional processor using transferred thin film circuits |
Aug. 12, 1997 |
| 5610094 |
Photoelectric conversion device |
Mar. 11, 1997 |
| 5427976 |
Method of producing a semiconductor on insulating substrate, and a method of forming a transistor thereon |
Jun. 27, 1995 |
| 5422302 |
Method for producing a three-dimensional semiconductor device |
Jun. 6, 1995 |
| 5409857 |
Process for production of an integrated circuit |
Apr. 25, 1995 |
| 5372959 |
Thin film transistor having a multi-layer stacked channel and its manufacturing method |
Dec. 13, 1994 |
| 5322816 |
Method for forming deep conductive feedthroughs |
Jun. 21, 1994 |
| 5312765 |
Method of fabricating three dimensional gallium arsenide microelectronic device |
May. 17, 1994 |
| 5306659 |
Reach-through isolation etching method for silicon-on-insulator devices |
Apr. 26, 1994 |
| 5130276 |
Method of fabricating surface micromachined structures |
Jul. 14, 1992 |
| 5124276 |
Filling contact hole with selectively deposited EPI and poly silicon |
Jun. 23, 1992 |
| 5120666 |
Manufacturing method for semiconductor device |
Jun. 9, 1992 |
| 5112765 |
Method of forming stacked tungsten gate PFET devices and structures resulting therefrom |
May. 12, 1992 |
| 5055425 |
Stacked solid via formation in integrated circuit systems |
Oct. 8, 1991 |
| 5049525 |
Iterative self-aligned contact metallization process |
Sep. 17, 1991 |
| 5032538 |
Semiconductor embedded layer technology utilizing selective epitaxial growth methods |
Jul. 16, 1991 |
| 4971925 |
Improved method of manufacturing a semiconductor device of the "semiconductor on insulator" type |
Nov. 20, 1990 |
| 4954458 |
Method of forming a three dimensional integrated circuit structure |
Sep. 4, 1990 |
| 4952526 |
Method for the fabrication of an alternation of layers of monocrystalline semiconducting material and layers of insulating material |
Aug. 28, 1990 |
| 4902637 |
Method for producing a three-dimensional type semiconductor device |
Feb. 20, 1990 |
| 4877752 |
3-D packaging of focal plane assemblies |
Oct. 31, 1989 |
| 4840923 |
Simultaneous multiple level interconnection process |
Jun. 20, 1989 |
| 4829018 |
Multilevel integrated circuits employing fused oxide layers |
May. 9, 1989 |
| 4797723 |
Stacked semiconductor device |
Jan. 10, 1989 |
| 4794092 |
Single wafer moated process |
Dec. 27, 1988 |
| 4793872 |
III-V Compound heteroepitaxial 3-D semiconductor structures utilizing superlattices |
Dec. 27, 1988 |
| 4771013 |
Process of making a double heterojunction 3-D I.sup.2 L bipolar transistor with a Si/Ge superlattice |
Sep. 13, 1988 |
| 4761681 |
Method for fabricating a semiconductor contact and interconnect structure using orientation dependent etching and thermomigration |
Aug. 2, 1988 |
| 4758534 |
Process for producing porous refractory metal layers embedded in semiconductor devices |
Jul. 19, 1988 |
| 4737470 |
Method of making three dimensional structures of active and passive semiconductor components |
Apr. 12, 1988 |
| 4696097 |
Poly-sidewall contact semiconductor device method |
Sep. 29, 1987 |
| 4692994 |
Process for manufacturing semiconductor devices containing microbridges |
Sep. 15, 1987 |
| 4679299 |
Formation of self-aligned stacked CMOS structures by lift-off |
Jul. 14, 1987 |
| 4663831 |
Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers |
May. 12, 1987 |
| 4661167 |
Method for manufacturing a monocrystalline semiconductor device |
Apr. 28, 1987 |
| 4660066 |
Structure for packaging focal plane imagers and signal processing circuits |
Apr. 21, 1987 |
| 4651408 |
Fabrication of stacked MOS devices utilizing lateral seeding and a plurality of separate implants at different energies |
Mar. 24, 1987 |
| 4649624 |
Fabrication of semiconductor devices in recrystallized semiconductor films on electrooptic substrates |
Mar. 17, 1987 |
| 4649627 |
Method of fabricating silicon-on-insulator transistors with a shared element |
Mar. 17, 1987 |
| 4612083 |
Process of fabricating three-dimensional semiconductor device |
Sep. 16, 1986 |
| 4603468 |
Method for source/drain self-alignment in stacked CMOS |
Aug. 5, 1986 |
| 4581623 |
Interlayer contact for use in a static RAM cell |
Apr. 8, 1986 |
| 4555843 |
Method of fabricating density intensive non-self-aligned stacked CMOS |
Dec. 3, 1985 |
| 4472792 |
Semiconductor memory |
Sep. 18, 1984 |
| 4467518 |
Process for fabrication of stacked, complementary MOS field effect transistor circuits |
Aug. 28, 1984 |
| 4424579 |
Mask programmable read-only memory stacked above a semiconductor substrate |
Jan. 3, 1984 |
