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Class Information
Number: 148/DIG.149
Name: Metal treatment > Silicon on iii-v
Description:










Patents under this class:

Patent Number Title Of Patent Date Issued
5354709 Method of making a lattice mismatched heterostructure optical waveguide Oct. 11, 1994
5244830 Method for manufacturing a semiconductor substrate having a compound semiconductor layer on a single-crystal silicon wafer Sep. 14, 1993
5081053 Method for forming a transistor having cubic boron nitride layer Jan. 14, 1992
4987095 Method of making unpinned oxide-compound semiconductor structures Jan. 22, 1991
4935385 Method of forming intermediate buffer films with low plastic deformation threshold using lattice mismatched heteroepitaxy Jun. 19, 1990
4910167 III-V Semiconductor growth initiation on silicon using TMG and TEG Mar. 20, 1990
4897367 Process for growing gallium arsenide on silicon substrate Jan. 30, 1990
4897361 Patterning method in the manufacture of miniaturized devices Jan. 30, 1990
4863877 Ion implantation and annealing of compound semiconductor layers Sep. 5, 1989
4830984 Method for heteroepitaxial growth using tensioning layer on rear substrate surface May. 16, 1989
4789421 Gallium arsenide superlattice crystal grown on silicon substrate and method of growing such crystal Dec. 6, 1988
4774205 Monolithic integration of silicon and gallium arsenide devices Sep. 27, 1988











 
 
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