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Class Information
Number: 148/DIG.147
Name: Metal treatment > Silicides
Description:










Patents under this class:
1 2 3 4

Patent Number Title Of Patent Date Issued
4227202 Dual plane barrier-type two-phase CCD Oct. 7, 1980
4224733 Ion implantation method Sep. 30, 1980
4180596 Method for providing a metal silicide layer on a substrate Dec. 25, 1979
4173063 Fabrication of a semiconductor component element having a Schottky contact and little series resistance utilizing special masking in combination with ion implantation Nov. 6, 1979
4169746 Method for making silicon on sapphire transistor utilizing predeposition of leads Oct. 2, 1979
4160987 Field effect transistors with polycrystalline silicon gate self-aligned to both conductive and non-conductive regions and fabrication of integrated circuits containing the transistors Jul. 10, 1979
4142926 Self-aligning double polycrystalline silicon etching process Mar. 6, 1979
4141022 Refractory metal contacts for IGFETS Feb. 20, 1979
4128670 Fabrication method for integrated circuits with polysilicon lines having low sheet resistance Dec. 5, 1978
4109372 Method for making an insulated gate field effect transistor utilizing a silicon gate and silicide interconnection vias Aug. 29, 1978
4106051 Semiconductor devices Aug. 8, 1978
4102733 Two and three mask process for IGFET fabrication Jul. 25, 1978
4080719 Method of manufacturing a semiconductor device and device manufactured according to the method Mar. 28, 1978
4042953 High temperature refractory metal contact assembly and multiple layer interconnect structure Aug. 16, 1977
3996656 Normally off Schottky barrier field effect transistor and method of fabrication Dec. 14, 1976
3933529 Process for the production of a pair of complementary field effect transistors Jan. 20, 1976

1 2 3 4










 
 
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