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Class Information
Number: 148/DIG.133
Name: Metal treatment > Reflow oxides and glasses
Description:










Patents under this class:
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Patent Number Title Of Patent Date Issued
5985745 Method of forming a via hole filled with a conducting material, and separater from a gate structure by an insulating material Nov. 16, 1999
5646075 Method for optimizing thermal budgets in fabricating semiconductors Jul. 8, 1997
5641704 Method of isolating active areas of a semiconductor substrate by shallow trenches and narrow trenches Jun. 24, 1997
5578522 Semiconductor device and method of fabricating same Nov. 26, 1996
5538906 Process for producing mask ROM Jul. 23, 1996
5538906 Process for producing mask ROM Jul. 23, 1996
5474955 Method for optimizing thermal budgets in fabricating semconductors Dec. 12, 1995
5470798 Moisture-free sog process Nov. 28, 1995
5461011 Method for reflowing and annealing borophosphosilicate glass to prevent BPO.sub.4 crystal formation Oct. 24, 1995
5455205 Method of producing semiconductor device Oct. 3, 1995
5449644 Process for contact hole formation using a sacrificial SOG layer Sep. 12, 1995
5409858 Method for optimizing thermal budgets in fabricating semiconductors Apr. 25, 1995
5384288 Method of forming a planarized insulation layer Jan. 24, 1995
5356834 Method of forming contact windows in semiconductor devices Oct. 18, 1994
5340774 Semiconductor fabrication technique using local planarization with self-aligned transistors Aug. 23, 1994
5314848 Method for manufacturing a semiconductor device using a heat treatment according to a temperature profile that prevents grain or particle precipitation during reflow May. 24, 1994
5284800 Method for preventing the exposure of borophosphosilicate glass to the ambient and stopping phosphorus ions from infiltrating silicon in a semiconductor process Feb. 8, 1994
5283203 Self-aligned contact process for complementary field-effect integrated circuits Feb. 1, 1994
5268333 Method of reflowing a semiconductor device Dec. 7, 1993
5258334 Process of preventing visual access to a semiconductor device by applying an opaque ceramic coating to integrated circuit devices Nov. 2, 1993
5244841 Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing Sep. 14, 1993
5234852 Sloped spacer for MOS field effect devices comprising reflowable glass layer Aug. 10, 1993
5204288 Method for planarizing an integrated circuit structure using low melting inorganic material Apr. 20, 1993
5169801 Method for fabricating a semiconductor device Dec. 8, 1992
5164340 Structure and method for contacts in CMOS devices Nov. 17, 1992
5120677 Method for making a semiconductor device by doping with arsenic, of at least 25 wt. % into a polysilicon layer Jun. 9, 1992
5112776 Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing May. 12, 1992
5110763 Process of fabricating multi-level wiring structure, incorporated in semiconductor device May. 5, 1992
5104482 Simultaneous glass deposition and viscoelastic flow process Apr. 14, 1992
5094984 Suppression of water vapor absorption in glass encapsulation Mar. 10, 1992
5077238 Method of manufacturing a semiconductor device with a planar interlayer insulating film Dec. 31, 1991
5054683 Method of bonding together two bodies with silicon oxide and practically pure boron Oct. 8, 1991
5047369 Fabrication of semiconductor devices using phosphosilicate glasses Sep. 10, 1991
5037773 Stacked capacitor doping technique making use of rugged polysilicon Aug. 6, 1991
5037777 Method for forming a multi-layer semiconductor device using selective planarization Aug. 6, 1991
5024965 Manufacturing high speed low leakage radiation hardened CMOS/SOI devices Jun. 18, 1991
5006484 Making a semiconductor device with contact holes having different depths Apr. 9, 1991
5004704 Method for manufacturing a semiconductor device having a phospho silicate glass layer as an interlayer insulating layer Apr. 2, 1991
4981809 Method of forming a mask pattern for the production of transistor Jan. 1, 1991
4962063 Multistep planarized chemical vapor deposition process with the use of low melting inorganic material for flowing while depositing Oct. 9, 1990
4948743 Method of manufacturing a semiconductor device Aug. 14, 1990
4920071 High temperature interconnect system for an integrated circuit Apr. 24, 1990
4892845 Method for forming contacts through a thick oxide layer on a semiconductive device Jan. 9, 1990
4879253 Method for fabricating a semiconductor device using a BPSG layer containing high concentrations of phosphorus and boron Nov. 7, 1989
4795722 Method for planarization of a semiconductor device prior to metallization Jan. 3, 1989
4795718 Self-aligned contact for MOS processing Jan. 3, 1989
4752591 Self-aligned contacts for bipolar process Jun. 21, 1988
4740483 Selective LPCVD tungsten deposition by nitridation of a dielectric Apr. 26, 1988
4740480 Method for forming a semiconductor device with trench isolation structure Apr. 26, 1988
4733291 Contact vias in semiconductor devices Mar. 22, 1988

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