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Class Information
Number: 148/DIG.102
Name: Metal treatment > Mask alignment
Description:










Patents under this class:
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Patent Number Title Of Patent Date Issued
6635549 Method of producing exposure mask Oct. 21, 2003
6465322 Semiconductor processing methods and structures for determining alignment during semiconductor wafer processing Oct. 15, 2002
6264165 Stage and supporting mechanism for supporting movable mirror on stage Jul. 24, 2001
6001703 Method of forming a fiducial for aligning an integrated circuit die Dec. 14, 1999
5982044 Alignment pattern and algorithm for photolithographic alignment marks on semiconductor substrates Nov. 9, 1999
5950093 Method for aligning shallow trench isolation Sep. 7, 1999
5882980 Process of forming bipolar alignment mark for semiconductor Mar. 16, 1999
5869386 Method of fabricating a composite silicon-on-insulator substrate Feb. 9, 1999
5843600 Use of sub divided pattern for alignment mark recovery after inter-level dielectric planarization Dec. 1, 1998
5830799 Method for forming embedded diffusion layers using an alignment mark Nov. 3, 1998
5814552 High step process for manufacturing alignment marks for twin-well integrated circuit devices Sep. 29, 1998
5786260 Method of fabricating a readable alignment mark structure using enhanced chemical mechanical polishing Jul. 28, 1998
5753391 Method of forming a resistor having a serpentine pattern through multiple use of an alignment keyed mask May. 19, 1998
5738961 Two-step photolithography method for aligning and patterning non-transparent layers Apr. 14, 1998
5712707 Edge overlay measurement target for sub-0.5 micron ground rules Jan. 27, 1998
5700732 Semiconductor wafer, wafer alignment patterns and method of forming wafer alignment patterns Dec. 23, 1997
5684333 Wafer structure in a semiconductor device manufacturing process Nov. 4, 1997
5580829 Method for minimizing unwanted metallization in periphery die on a multi-site wafer Dec. 3, 1996
5545576 Method for manufacturing a thin film transistor panel Aug. 13, 1996
5529595 Method of positioning elements of an optical integrated circuit Jun. 25, 1996
5527726 Self-aligned thin-film transistor constructed using lift-off technique Jun. 18, 1996
5523258 Method for avoiding lithographic rounding effects for semiconductor fabrication Jun. 4, 1996
5510286 Method for forming narrow contact holes of a semiconductor device Apr. 23, 1996
5503962 Chemical-mechanical alignment mark and method of fabrication Apr. 2, 1996
5496777 Method of arranging alignment marks Mar. 5, 1996
5482893 Method for producing semiconductor device having alignment mark Jan. 9, 1996
5470782 Method for manufacturing an integrated circuit arrangement Nov. 28, 1995
5468664 Method of making semiconductor device with alignment marks Nov. 21, 1995
5466640 Method for forming a metal wire of a semiconductor device Nov. 14, 1995
5466640 Method for forming a metal wire of a semiconductor device Nov. 14, 1995
5360761 Method of fabricating closely spaced dual diode lasers Nov. 1, 1994
5346858 Semiconductor non-corrosive metal overcoat Sep. 13, 1994
5328857 Method of forming a bilevel, self aligned, low base resistance semiconductor structure Jul. 12, 1994
5316966 Method of providing mask alignment marks May. 31, 1994
5283205 Method for manufacturing a semiconductor device on a substrate having an anisotropic expansion/contraction characteristic Feb. 1, 1994
5270255 Metallization process for good metal step coverage while maintaining useful alignment mark Dec. 14, 1993
5268313 Method of manufacturing a semiconductor device having a spacer Dec. 7, 1993
5258317 Method for using a field implant mask to correct low doping levels at the outside edges of the base in a walled-emitter transistor structure Nov. 2, 1993
5157002 Method for forming a mask pattern for contact hole Oct. 20, 1992
5147812 Fabrication method for a sub-micron geometry semiconductor device Sep. 15, 1992
5132236 Method of semiconductor manufacture using an inverse self-aligned mask Jul. 21, 1992
5106782 Method of manufacturing a semiconductor device Apr. 21, 1992
5106767 Process for fabricating low capacitance bipolar junction transistor Apr. 21, 1992
5106432 Wafer alignment mark utilizing parallel grooves and process Apr. 21, 1992
5053348 Fabrication of self-aligned, T-gate HEMT Oct. 1, 1991
5051374 Method of manufacturing a semiconductor device with identification pattern Sep. 24, 1991
5034346 Method for forming shorting contact for semiconductor which allows for relaxed alignment tolerance Jul. 23, 1991
5026660 Methods for making photodectors Jun. 25, 1991
4981529 Semiconductor substrate provided with marks for alignment even under a resist film Jan. 1, 1991
4936930 Method for improved alignment for semiconductor devices with buried layers Jun. 26, 1990

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