| Patent Number |
Title Of Patent |
Date Issued |
| 7453312 |
Voltage regulator outputting positive and negative voltages with the same offsets |
November 18, 2008 |
| A voltage regulator has a first charge circuit, a second charge circuit, and a control circuit. The control circuit has five input terminals and two output terminals. The five input terminals are respectively coupled to a reference voltage, a first voltage source, a second voltage source |
| 7450418 |
Non-volatile memory and operating method thereof |
November 11, 2008 |
| An operating method of a non-volatile memory is provided. The non-volatile memory includes plural memory cells. Each memory cell includes a charge storage structure, a gate, and a source and a drain disposed in the well on the both sides of the gate. During an erasing operation, a first |
| 7447082 |
Method for operating single-poly non-volatile memory device |
November 4, 2008 |
| A single-poly non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly non-volatile memory cell includes an ion well, a gate formed on the ion well, a gate dielectric layer between the gate and the ion well, a |
| 7433243 |
Operation method of non-volatile memory |
October 7, 2008 |
| A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive t |
| 7427889 |
Voltage regulator outputting positive and negative voltages with the same offsets |
September 23, 2008 |
| A voltage regulator has a first charge circuit, a second charge circuit, and a control circuit. The control circuit has five input terminals and two output terminals. The five input terminals are respectively coupled to a reference voltage, a first voltage source, a second voltage source |
| 7417897 |
Method for reading a single-poly single-transistor non-volatile memory cell |
August 26, 2008 |
| A method for operating a single-poly, single-transistor (1-T) non-volatile memory (NVM) cell. The NVM cell includes a gate on a P substrate, a gate dielectric layer, an N drain region and an N source region. N channel is defined between the N drain region and N source region. The NVM cel |
| 7405972 |
Non-volatile memory array |
July 29, 2008 |
| A non-volatile memory array including a plurality of memory units is provided. Each memory unit is serially connected with a select transistor and a memory cell. A source region is next to the select transistor while a drain region is next to the memory cell. The drain lines are arranged |
| 7394306 |
Regulator circuit |
July 1, 2008 |
| A regulator circuit having a voltage output terminal is provided. The regulator circuit includes a current mirror module, a plurality of source followers, and a switch. The current module receives a driving voltage, and has a first current terminal coupled to a driving current and a |
| 7385855 |
Nonvolatile memory device having self reprogramming function |
June 10, 2008 |
| A nonvolatile memory device having a self reprogramming function is provided. The nonvolatile memory device includes a memory cell, a first transistor, a second transistor, and a latch circuit. The memory cell is for data storage. The first transistor receives a reading control signal |
| 7382180 |
Reference voltage source and current source circuits |
June 3, 2008 |
| The voltage source and current source circuits including an amplifier, a first current mirror circuit, a first PMOS transistor, a second current mirror circuit and a NMOS transistor are provided. The amplifier has a positive input terminal and a negative input terminal coupled to the |
| 7327621 |
Current sense amplifier with lower sensing error rate by using smaller sensing current differenc |
February 5, 2008 |
| A sensing amplifier comprising a program cell current sensing circuit, an erase cell current sensing circuit and a latch circuit is provided. Each of the program and erase cell current sensing circuits further comprises a plurality of program/erase memory cells, a first NMOS transistor, |
| 7319610 |
MTP storage medium and access algorithm method with traditional OTP |
January 15, 2008 |
| A method for performing multi-programmable function with one-time programmable (OTP) memories includes: generating a newest word in a OTP memory array; receive a word-to-be-record; comparing the newest word and the word-to-be-record; and according to a result, recording bit informati |
| 7288964 |
Voltage selective circuit of power source |
October 30, 2007 |
| A voltage selective circuit of a power source having a first voltage and a second voltage of the present invention includes a selective switch module, a high voltage bias module, a level shift module and a high voltage selective module. The selective switch module includes two first |
| 7262457 |
Non-volatile memory cell |
August 28, 2007 |
| A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well |
| 7254086 |
Method for accessing memory |
August 7, 2007 |
| The present invention provides a method for accessing a memory. The memory contains M one-time programmable memory blocks, and each has a first memory sector and a second memory sector. The method includes: selecting a first target memory block and reading the first target memory block. |
| 7250654 |
Non-volatile memory device |
July 31, 2007 |
| A single-poly non-volatile memory device invented to integrate into logic process is disclosed. This non-volatile memory device includes a memory cell unit comprising a PMOS access transistor that is serially connected to a PMOS storage transistor formed in a cell array area, and, in a |
| 7244985 |
Non-volatile memory array |
July 17, 2007 |
| A non-volatile memory array including memory units which are arranged in a row/column array is provided. Source lines are arranged in parallel in the column direction and connect to the source regions of the memory units in the same column. Bit lines are arranged in parallel in the row |
| 7218165 |
Boost circuit |
May 15, 2007 |
| A boost circuit comprising a first level shifter and a switch circuit is provided. The first level shifter outputs either an output voltage of the boost circuit or a first bias voltage according to a boost control signal. The switch circuit determines whether to transmit a second bias |
| 7215043 |
Power supply voltage switch circuit |
May 8, 2007 |
| A power supply voltage switch circuit for selecting a power supply voltage of an integrated circuit according to a first control signal. The power supply voltage switch circuit contains a high voltage selecting module for generating an output voltage according to the higher of a first an |
| 7209392 |
Single poly non-volatile memory |
April 24, 2007 |
| An erasable programmable non-volatile memory cell encompasses an ion well; a first select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; a first floating gate transistor having a drain, a source coupled t |
| 7172940 |
Method of fabricating an embedded non-volatile memory device |
February 6, 2007 |
| A method of fabricating a non-volatile memory based on SONOS is disclosed. By masking the peripheral circuit area with a reverse ONO photoresist layer, the residual ONO layer that is not covered by a gate within the memory array area is etched away to expose the substrate. After the |
| 7123077 |
Four-phase charge pump circuit with reduced body effect |
October 17, 2006 |
| A charge pump circuit has an input stage, an output stage and multiple boosting stages coupled between the input stage and the output stage. The boosting stages are driven by four phase clock signals. Each boosting stage has two branch charge pumps, wherein each branch charge pump at |
| 7020036 |
Memory unit with sensing current stabilization |
March 28, 2006 |
| A memory unit with sensing current stabilization includes: a memory cell; a reference cell for providing a reference current; a current mirror coupled to the memory cell and the reference cell for generating a differential current according to the reference current and a cell current |
| 6975545 |
Non-volatile memory cell |
December 13, 2005 |
| A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well |
| 6972606 |
Delay circuits and related apparatus for extending delay time by active feedback elements |
December 6, 2005 |
| A delay circuit and related apparatus for providing a longer delay time, such that when a level of an input signal changes, a level of an output signal changes accordingly after the predetermined delay time. The delay circuit has a storage unit, a current generator, a voltage generator f |
| 6958597 |
Voltage generating apparatus with a fine-tune current module |
October 25, 2005 |
| Voltage generating apparatus includes a positive temperature coefficient current generating module, a negative temperature coefficient current generating module, a fine-tune current module and a voltage output module. The function of the positive temperature coefficient current generatin |
| 6952369 |
Method for operating a NAND-array memory module composed of P-type memory cells |
October 4, 2005 |
| A method for writing a memory module includes providing a plurality of memory cells, applying a first transmission line voltage to the first transmission line of the column of a memory cell, turning on a P-type channel of a memory cell between the memory cell to be written and the fi |
| 6952129 |
Four-phase dual pumping circuit |
October 4, 2005 |
| A four-phase dual pumping circuit has a number of stages according to the required output voltage based on an input voltage. Each stage has a first pumping unit and a second pumping unit that are mirror and identical to each other and electrically coupled to each other. The dual pumping |
| 6922363 |
Method for operating a NOR-array memory module composed of P-type memory cells |
July 26, 2005 |
| A method for writing a memory module includes providing a plurality of memory cells. Each memory cell includes a substrate, a P-type drain and source, a gate, and a stack dielectric layer which stores 2-bit data. Memory cells are arranged in a matrix with gates and sources on the same |
| 6920067 |
Integrated circuit embedded with single-poly non-volatile memory |
July 19, 2005 |
| A system on chip (SOC) contains a core circuit and an input/output (I/O) circuit embedded with an array of single-poly erasable programmable read only memory cells, each of which comprises a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS |
| 6914842 |
Pure CMOS latch-type fuse circuit |
July 5, 2005 |
| An option fuse circuit, which can be viewed as a latch-type option fuse circuit, is manufactured with a standard single-poly CMOS manufacturing process. The option fuse circuit includes a non-volatile memory module for storing a logic bit in a data program status, a data control circuit |
| 6914825 |
Semiconductor memory device having improved data retention |
July 5, 2005 |
| A NVM device encompasses a MOS select transistor including a select gate electrically connected to a word line, a first source doping region electrically connected to a source line, and a first drain doping region. A MOS floating gate transistor is serially electrically connected to the |
| 6888400 |
Charge pump circuit without body effects |
May 3, 2005 |
| A charge pump circuit has input and output nodes, a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. A drain of the first transistor and a drain of the second transistor are connected to the input node. A source of the second trans |
| 6888190 |
EEPROM with source line voltage stabilization mechanism |
May 3, 2005 |
| A low-voltage nonvolatile memory array includes an N type semiconductor substrate having a memory region. A deep P well is formed in the semiconductor substrate. A cell N well is located within the memory region in the semiconductor substrate. The cell N well is situated above the deep |
| 6885587 |
Single poly embedded EPROM |
April 26, 2005 |
| A novel structure of nonvolatile memory is disclosed. The non-volatile memory includes two serially connected PMOS transistors. The characteristic of the devices is that bias is not necessary to apply to the floating gate during the programming mode. Thus, the control gate is omitted |
| 6882574 |
Single poly UV-erasable programmable read only memory |
April 19, 2005 |
| An erasable programmable read only memory includes two serially connected P-type metal-oxide semiconductor (MOS) transistors, wherein a first P-type MOS transistor acts as select transistor, a gate of the first P-type MOS transistor is coupled to select gate voltage, a first node of the |
| 6850442 |
Flash memory with sensing amplifier using load transistors driven by coupled gate voltages |
February 1, 2005 |
| A memory including a plurality of memory cells, a sensing load, a reference load, a control circuit and a comparator. Each of the memory cells can store a bit data and provide a driving current according to the bit data. The sensing load is driven by the driving current and a driving vol |
| 6847087 |
Bi-directional Fowler-Nordheim tunneling flash memory |
January 25, 2005 |
| A low-voltage nonvolatile memory array includes a cell well of a first conductivity type formed in a substrate; columns of buried bit lines of a second conductivity type formed within the cell well, wherein columns of the buried bit lines are isolated from each other and each is further |
| 6842374 |
Method for operating N-channel electrically erasable programmable logic device |
January 11, 2005 |
| An electrically erasable programmable logic device (EEPLD) contains a P-type substrate. A first N-type doped region is disposed in the P-type substrate. A first gate, which is used to store data, overlies the P-type substrate and is adjacent to the first N-type doped region. A second |
| 6829166 |
Method for controlling a non-volatile dynamic random access memory |
December 7, 2004 |
| A method for controlling a non-volatile dynamic random access memory provides a non-volatile dynamic random access memory having a storage unit and a control unit. The storage unit has a floating gate for storing charges and a control gate for receiving an operating voltage to determine |
| 6822286 |
Cmos-compatible read only memory and method for fabricating the same |
November 23, 2004 |
| A CMOS-compatible read only memory (ROM) includes a first single-poly PMOS transistor that is serially electrically connected to a second single-poly PMOS transistor for recording digital data "1" or digital data "0". The first and second single-poly PMOS transistors are both formed on a |
| 6819620 |
Power supply device with reduced power consumption |
November 16, 2004 |
| A power supply used for providing a flash memory with an operating voltage has a plurality of memory blocks and a plurality of decoders corresponding to the memory blocks. Each memory block has a plurality of memory cells for storing binary data. Each decoder is used for selecting memory |
| 6819594 |
Electrically erasable programmable logic device |
November 16, 2004 |
| An electrically erasable programmable logic device includes a P-type substrate, a first N-type doped region located inside the P-type substrate, and a first gate located on the P-type substrate. The first gate is adjacent to the first N-type doped region, is in a floating state, and |
| 6812083 |
Fabrication method for non-volatile memory |
November 2, 2004 |
| A fabrication method for a non-volatile memory includes providing a first metal oxide semiconductor (MOS) transistor having a control gate and a second MOS transistor having a source, a drain, and a floating gate. The first MOS transistor and the second MOS transistor are formed on a wel |
| 6809603 |
Ring oscillator having a stable output signal without influence of MOS devices |
October 26, 2004 |
| A ring oscillator having a stable output signal without influence of MOS devices is disclosed. The ring-oscillator has a bias circuit to drive a plurality of delay cells. The bias circuit has a first loading unit with a p-n junction, a second loading unit with a p-n junction, and a resis |
| 6801456 |
Method for programming, erasing and reading a flash memory cell |
October 5, 2004 |
| A method for programming PMOS single transistor flash memory cells through channel hot carrier induced hot electron injection mechanism is disclosed. The PMOS single transistor flash memory cell includes an ONO stack layer situated on an N-well of a semiconductor substrate, a P.sup.+ pol |
| 6787419 |
Method of forming an embedded memory including forming three silicon or polysilicon layers |
September 7, 2004 |
| A wafer has a substrate defined with a first region and a second region. An ONO layer, a first silicon layer, and a silicon nitride layer are formed on the substrate in sequence. Then the ONO layer, the first silicon layer, and the silicon nitride layer disposed on the second region are |
| 6775189 |
Option fuse circuit using standard CMOS manufacturing process |
August 10, 2004 |
| An option fuse circuit using standard CMOS manufacturing processes includes a latch for latching signals, which includes a first node and a second node. The option fuse circuit also includes a comparator, which includes two input nodes and an output node. The comparator receives signals |
| 6770950 |
Non-volatile semiconductor memory structure |
August 3, 2004 |
| A non-volatile semiconductor memory cell structure and method of manufacture. The method includes the steps of forming a shallow first-type well layer, a second-type well layer and a deep first-type well layer over a substrate, forming stack gates over the shallow first-type well layer |
| 6768678 |
Data sensing method used in a memory cell circuit |
July 27, 2004 |
| A device and method for data sensing includes turning off a first and a second program switches while turning on a first and a second switches in order to output a first current corresponding to a first data from a first memory cell to a biasing circuit, also to output a second current |
