| Patent Number |
Title Of Patent |
Date Issued |
| RE40423 |
Multiport RAM with programmable data port configuration |
July 8, 2008 |
| A RAM with programmable data port configuration provides for programmable configuration of RAM data ports, and in the case of a multiport RAM, for independent programmable configuration of each data port. A single programmable RAM cell can be utilized in a variety of data port config |
| RE37195 |
Programmable switch for FPGA input/output signals |
May 29, 2001 |
| A programmable switch for a field programmable gate array (FPGA) allows a user to reconfigure or partly reconfigure the FPGA from within the FPGA, allows an addressable configuration memory to be addressed through a set of pins for configuration and through user logic for reconfiguration |
| RE34808 |
TTL/CMOS compatible input buffer with Schmitt trigger |
December 20, 1994 |
| A TTL/CMOS compatible input buffer circuit comprises a Schmitt trigger input buffer stage and a reference voltage generator. In the TTL mode, the reference voltage generator supplies a reference voltage having a level that forces the trigger point of the Schmitt trigger to a predetermine |
| RE34444 |
Programmable logic device |
November 16, 1993 |
| A programmable logic device architecture having a matrix of smaller functional units, each of which being a programmable logic array, and a set of fixed conductive lines connected to the functional unit inputs and outputs, the conductive lines forming programmable interconnection mat |
| RE34363 |
Configurable electrical circuit having configurable logic elements and configurable interconnect |
August 31, 1993 |
| A configurable logic array comprises a plurality of configurable logic elements variably interconnected in response to control signals to perform a selected logic function. Each configurable logic element in the array is in itself capable of performing any one of a plurality of logic fun |
| 7620942 |
Method and system for parameterization of imperative-language functions intended as hardware gen |
November 17, 2009 |
| A method (100) of translating an imperative language function into a parameterized hardware component can include the steps of using (102) formal imperative function arguments to represent at least one among a component input port and a component parameter and distinguishing (104) be |
| 7620929 |
Programmable logic device having a programmable selector circuit |
November 17, 2009 |
| A PLD is configurable to efficiently implement a wide variety of user functions. The PLD includes a programmable interconnect circuit, programmable logic circuits, one-bit registers, selector circuits, and input/output blocks. The programmable interconnect circuit is configurable to |
| 7620927 |
Method and apparatus for circuit design closure using partitions |
November 17, 2009 |
| A method of implementing a circuit design can include selecting the circuit design to be implemented, wherein the circuit design comprises a plurality of partitions, and receiving a user input specifying a value of a partition property. The partition property can be associated with a |
| 7620926 |
Methods and structures for flexible power management in integrated circuits |
November 17, 2009 |
| Structures and methods of efficiently implementing power management in integrated circuits (ICs). An IC includes columns of logic blocks and columns of power management blocks (PMBs). The columns of PMBs and logic blocks are placed alternately across the IC, with each PMB being coupled |
| 7620923 |
Run-time efficient methods for routing large multi-fanout nets |
November 17, 2009 |
| A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a plurality of loads and identifying each region of the IC which does not include at least o |
| 7620883 |
Techniques for mitigating, detecting, and correcting single event upset effects |
November 17, 2009 |
| SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter cir |
| 7620875 |
Error correction code memory system with a small footprint and byte write operation |
November 17, 2009 |
| A method, apparatus and program storage device that provides an error correction code memory system with a small footprint and byte write operation. A memory controller virtualizes the memory controller interface, multiplexes ECC data onto the same pins as data, and stores replicated |
| 7620863 |
Utilizing multiple test bitstreams to avoid localized defects in partially defective programmabl |
November 17, 2009 |
| Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different prog |
| 7620862 |
Method of and system for testing an integrated circuit |
November 17, 2009 |
| The methods and circuits of the present invention relate to testing integrated circuits. According to one aspect of the invention, a method of testing an integrated circuit is disclosed. The method comprises the steps of coupling test equipment to the integrated circuit; coupling a t |
| 7620795 |
Controller for a processor having internal memory |
November 17, 2009 |
| Apparatus and method for a microcontroller are described. The microcontroller includes a microprocessor having storage and bussing for accessing the storage. A portion of the bussing is coupled to hardwired operation codes, and a portion of the storage is for storing code. The hardwi |
| 7620780 |
Multiprocessor system with cache controlled scatter-gather operations |
November 17, 2009 |
| Dynamic cache architecture for a multi-processor array. The system includes a plurality of processors, with at least one of the processors configured as a parent processor, and at least one of the processors configured as a child processor. A data cache is coupled to the parent proce |
| 7620752 |
Circuit for and method of processing data input to a first-in first-out memory |
November 17, 2009 |
| A method of processing data input to a first-in first-out memory is disclosed. The method comprises steps of receiving input data words from a pipeline stage at an input of the first-in first-out memory; receiving data valid bits associated with the pipeline stage; generating a count |
| 7620121 |
DC balance compensation for AC-coupled circuits |
November 17, 2009 |
| A receiver has a first input port and a second input port both coupled to a differential amplifier through first and second input capacitors. A bias circuit coupled to the core side of the first input capacitor and to the core side of the second input capacitor is configured to provide a |
| 7619486 |
Method for detecting and compensating for temperature effects |
November 17, 2009 |
| An integrated circuit fabricated in a multiple oxide process can be used to provide a temperature-insensitive circuit. The temperature-insensitive circuit can be a ring oscillator; this ring oscillator can be used as a low-cost integrated reference frequency to monitor and to modify the |
| 7619442 |
Versatile bus interface macro for dynamically reconfigurable designs |
November 17, 2009 |
| Method and apparatus for module design in a PLD is described. In one example, a PLD includes a reconfigurable module, a static module, and at least one logic interface macro. The reconfigurable module includes a signal interface and is configured for active partial reconfiguration. T |
| 7619441 |
Apparatus for interconnecting stacked dice on a programmable integrated circuit |
November 17, 2009 |
| An apparatus for interconnecting stacked dice on a programmable integrated circuit is described. In one example, an integrated circuit die comprises a programmable integrated circuit that includes first and second interface tiles. The first interface tile is in electrical communication |
| 7619438 |
Methods of enabling the use of a defective programmable device |
November 17, 2009 |
| Methods of enabling the use of defective programmable devices. The method comprises performing functional testing for each programmable device of a plurality of programmable devices; identifying each programmable device of the plurality of programmable devices having a defective portion |
| 7619298 |
Method and apparatus for reducing parasitic capacitance |
November 17, 2009 |
| A method and apparatus for reducing parasitic capacitance. A P-well blocked layer is formed directly beneath a parasitic device. The P-well blocked layer significantly increases the resistance underneath the parasitic device. The resistance of the P-well blocked layer, in effect, par |
| 7617472 |
Regional signal-distribution network for an integrated circuit |
November 10, 2009 |
| Signal distribution of a regional signal is described. An integrated circuit includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The |
| 7617471 |
Processor event interface for programmable integrated circuit based circuit designs |
November 10, 2009 |
| A method of implementing a circuit design on a programmable integrated circuit can include displaying a list of at least one memory of the circuit design that is associated with the processor. A plurality of attributes of an event for the processor can be received. The plurality of a |
| 7614025 |
Method of placement for iterative implementation flows |
November 3, 2009 |
| A method of implementing a circuit design in a target device can include identifying routing information for a circuit design that has been at least partially implemented. A plurality of empty sites of the target device within which the circuit design is to be implemented can be iden |
| 7614022 |
Testing for bridge faults in the interconnect of programmable integrated circuits |
November 3, 2009 |
| Apparatus and methods of testing for bridge faults in nets of the interconnect of a programmable integrated circuit. Each net is sourced by a function generator (e.g., a look up table) configured as a clocked shift register. For each net group, shift registers connecting nets in the |
| 7613990 |
Method and system for a multi-channel add-compare-select unit |
November 3, 2009 |
| A circuit for a multi-channel add-compare-select unit is disclosed. The circuit includes a compare unit and a datapath. The datapath is coupled to the compare unit, and includes a number of adder units, a selection unit (which is coupled to the adder units), and a number of clocked s |
| 7610573 |
Implementation of alternate solutions in technology mapping and placement |
October 27, 2009 |
| A computer-implemented method of implementing a circuit design within a target integrated circuit (IC) can include, during technology mapping of the circuit design, determining a plurality of implementations of at least one sub-circuit of the circuit design and placing the circuit de |
| 7610534 |
Determining a length of the instruction register of an unidentified device on a scan chain |
October 27, 2009 |
| Methods and systems are provided for determining a total length of instruction registers. A data shift of a scan chain determines whether each device in the scan chain is an identified device. An overall length of the instruction registers of the devices is determined from an instruc |
| 7610519 |
Vector generation for codes through symmetry |
October 27, 2009 |
| Apparatus for vector generation is described. A vector generator is associated with a discrete power series symmetric about at least one term and configured to provide vectors, such as QSvectors for a Turbo Code for example. The vectors are each provided in separate portions as a first |
| 7610453 |
Reordering each array in a sequence of arrays |
October 27, 2009 |
| Each array in a sequence of arrays is reordered. A first port receives in a first serial order a number of values in each array in the sequence and a second port transmits the values in a different second serial order. For each value in each array in the sequence, the address generator |
| 7609087 |
Integrated circuit device programming with partial power |
October 27, 2009 |
| A separate program power input is provided to a programmable logic array's memory to permit it to be programmed independently of printed circuit board power. Means are provided to isolate the program power input from the array's programmable logic circuit. Means are further provided to |
| 7608931 |
Interconnect array formed at least in part with repeated application of an interconnect pattern |
October 27, 2009 |
| An interconnect array formed at least in part using repeated application of an interconnect pattern is described. The interconnect pattern has at least ten interconnect locations. One of the ten interconnect locations is for a power interconnect. Another one of the ten interconnect l |
| 7607025 |
Methods of intrusion detection and prevention in secure programmable logic devices |
October 20, 2009 |
| Methods of securing a programmable logic device (PLD) when an intrusion attempt is detected, e.g., methods of erasing sensitive data from the PLD or disabling configuration of the PLD in response to an attack. For example, when an attempt is made to configure the PLD with an unauthor |
| 7606694 |
Framework for cycle accurate simulation |
October 20, 2009 |
| A system for performing cycle accurate simulation of a circuit design can include a plurality of cycle accurate models, wherein each cycle accurate model is a software object representation of a hardware function, and a scheduler configured to execute each cycle accurate model at clock c |
| 7605604 |
Integrated circuits with novel handshake logic |
October 20, 2009 |
| Integrated circuits (ICs) having novel handshake logic are provided. An IC includes a ready multiplexer, an acknowledge demultiplexer, a C-element coupled to the ready multiplexer and the acknowledge demultiplexer, a logic gate, and a storage element (e.g., a latch). The logic gate has a |
| 7605460 |
Method and apparatus for a power distribution system |
October 20, 2009 |
| A method and apparatus is provided to reduce the spreading inductance and increase the distributed capacitance of power planes within the power distribution system of a semiconductor package substrate. In one embodiment, pre-fabricated copper-clad laminate (CCL) structures are utiliz |
| 7605458 |
Method and apparatus for integrating capacitors in stacked integrated circuits |
October 20, 2009 |
| Method and apparatus for integrating capacitors in stacked integrated circuits are described. One aspect of the invention relates to a semiconductor assembly having a carrier substrate, a plurality of integrated circuit dice, and at least one metal-insulator-metal (MIM) capacitor. Th |
| 7603646 |
Method and apparatus for power optimization using don't care conditions of configuration bits in |
October 13, 2009 |
| Various approaches for generating an implementation of an electronic circuit design are disclosed. In one approach, one or more configuration bits that have don't care conditions are identified for a LUT block of a design. A dynamic power state for a subset of a first level of logic |
| 7603599 |
Method to test routed networks |
October 13, 2009 |
| Testing of routing resources in a path between network nodes is provided using simpler nodes to replace more complex IP modules which could be programmed into an FPGA after the routing resources are tested. Further, when it is impractical to generate a pattern from a source node S for |
| 7600210 |
Method and apparatus for modular circuit design for a programmable logic device |
October 6, 2009 |
| Method, apparatus, and computer readable medium for modular circuit design for a programmable logic device (PLD) is described. In one example, a circuit design is captured. The circuit design includes a plurality of modules and one or more logic interface macros positioned on a floorplan |
| 7600204 |
Method for simulation of negative bias and temperature instability |
October 6, 2009 |
| An apparatus and method to accurately simulate negative bias and temperature instability (NBTI) and its effect. According to a first simulation method, a simulation netlist is automatically scanned for any P-type devices that are in a conductive state after application of an initial |
| 7599431 |
Combined decision feedback equalization and linear equalization |
October 6, 2009 |
| A communication system includes a transmitter, a communication channel, and a receiver. The transmitter includes a pre-emphasis module, a summing module, a line driver, and a decision feedback pre-emphasis (DFP) module to produce a pre-emphasized serial stream of data based on a comm |
| 7599430 |
Fading channel modeling |
October 6, 2009 |
| Simulation of noise and, more particularly, a coefficient generator for channel modeling, is described. A spectrum memory is for storing sets of constants for respective harmonics. At least one phase noise source is configured for generating phase noise. An Inverse Fourier Transform bloc |
| 7599299 |
Dynamic reconfiguration of a system monitor (DRPORT) |
October 6, 2009 |
| Method and apparatus for a dynamically reconfigurable system monitor (20) are described. A system monitor (20) has registers (206) accessible via a reconfiguration port (201). At least one of the registers may be dynamically reconfigured via the reconfiguration port (201) to select a |
| 7598768 |
Method and apparatus for dynamic port provisioning within a programmable logic device |
October 6, 2009 |
| A method and apparatus to allow dynamic port provisioning of communication ports within a Programmable Logic Device (PLD). The dynamic port provisioning combines configuration of serial Input/Output (I/O) devices with simultaneous reconfiguration of a portion of programmable logic re |
| 7598749 |
Integrated circuit with fuse programming damage detection |
October 6, 2009 |
| An integrated circuit with an efuse having an efuse link includes a damage detection structure disposed in relation to the efuse so as to detect damage in the IC resulting from programming the efuse. Damage sensing circuitry is optionally included on the IC. Embodiments are used in e |
| 7598727 |
Probe card head protection device for wafer sort set up |
October 6, 2009 |
| A protective mechanism for a probe card cover to prevent the probe card cover or attachment screws extending from the probe card cover from striking a wafer in a test system if the probe card is installed without removing the cover. The protective mechanism includes an elongate member |
| 7594212 |
Automatic pin placement for integrated circuits to aid circuit board design |
September 22, 2009 |
| A computer-implemented method of placing input/output (I/O) pins of a circuit design for an integrated circuit (IC) can include selecting a bus from a plurality of buses, where the selected bus includes a plurality of I/O pins and is part of an interface, and, for each of a plurality of |
