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Xilinx, Inc. Patents
Xilinx, Inc.
San Jose, CA
No. of patents:

Patent Number Title Of Patent Date Issued
RE40423 Multiport RAM with programmable data port configuration July 8, 2008
A RAM with programmable data port configuration provides for programmable configuration of RAM data ports, and in the case of a multiport RAM, for independent programmable configuration of each data port. A single programmable RAM cell can be utilized in a variety of data port config
RE37195 Programmable switch for FPGA input/output signals May 29, 2001
A programmable switch for a field programmable gate array (FPGA) allows a user to reconfigure or partly reconfigure the FPGA from within the FPGA, allows an addressable configuration memory to be addressed through a set of pins for configuration and through user logic for reconfiguration
RE34808 TTL/CMOS compatible input buffer with Schmitt trigger December 20, 1994
A TTL/CMOS compatible input buffer circuit comprises a Schmitt trigger input buffer stage and a reference voltage generator. In the TTL mode, the reference voltage generator supplies a reference voltage having a level that forces the trigger point of the Schmitt trigger to a predetermine
RE34444 Programmable logic device November 16, 1993
A programmable logic device architecture having a matrix of smaller functional units, each of which being a programmable logic array, and a set of fixed conductive lines connected to the functional unit inputs and outputs, the conductive lines forming programmable interconnection mat
RE34363 Configurable electrical circuit having configurable logic elements and configurable interconnect August 31, 1993
A configurable logic array comprises a plurality of configurable logic elements variably interconnected in response to control signals to perform a selected logic function. Each configurable logic element in the array is in itself capable of performing any one of a plurality of logic fun
8587337 Method and apparatus for capturing and synchronizing data November 19, 2013
An embodiment of a technique to capture and locally synchronize data is disclosed. The technique includes receiving first and second signals through a first interface, and receiving a third signal through a second interface where the third signal is unsynchronized with respect to the
8583944 Method and integrated circuit for secure encryption and decryption November 12, 2013
In one embodiment, a circuit arrangement for performing cryptographic operations is provided. The circuit includes a substitution block, a cryptographic circuit coupled to the substitution block, and a balancing circuit coupled to the substitution block. The substitution block includ
8576641 Method of and circuit for providing non-volatile memory in an integrated circuit November 5, 2013
A method of providing non-volatile memory in an integrated circuit is disclosed. The method may comprise storing a plurality of data blocks in volatile memory elements of the integrated circuit, wherein each data block of the plurality of data blocks comprises a plurality of data bits;
8572528 Method and apparatus for analyzing a design of an integrated circuit using fault costs October 29, 2013
In one embodiment, a method and apparatus for analyzing a design of an integrated circuit (IC) are disclosed. For example, the method parses a netlist file of the IC where a module of the IC is parsed into a plurality of sub-modules in accordance with a hierarchical structure. The me
8572432 Method and apparatus for processing an event notification in a concurrent processing system October 29, 2013
In one embodiment, a concurrent processing system is disclosed. For example, in one embodiment of the present invention, a concurrent processing system, comprises a first processing element comprising a first monitor module, a second processing element in communication with the first
8572153 Multiplier circuit configurable for real or complex operation October 29, 2013
A configurable multiplier circuit for multiplying both real and complex numbers is included in a PLD. In one embodiment, the circuit includes two adder trees. Multiplexers are used such that a conventional multiplier component is not required. The circuit is programmable to operate in on
8572150 Parameterization of a CORDIC algorithm for providing a CORDIC engine October 29, 2013
Parameterization of a CORDIC algorithm for providing a CORDIC engine is described. An aspect of the invention is a method in a digital processing system for generation of the CORDIC engine. Numbers of fractional output bits for a user-defined numerical result format are obtained. The num
8572148 Data reorganizer for fourier transformation of parallel data streams October 29, 2013
A data reorganizer for Fourier Transforms, both forward and inverse, of multiple parallel data streams input to an integrated circuit, and method for use thereof, are described. The data reorganizer has a k input commutator, for k a positive integer greater than zero; an address gene
8564330 Methods and systems for high frequency clock distribution October 22, 2013
In accordance with some embodiments, a method for high frequency clock distribution in a VLSI system includes splitting an original master clock signal into one or more pairs of lower-frequency sub-clocks for a destination in the VLSI system, distributing each lower-frequency sub-clo
8564023 Integrated circuit with MOSFET fuse element October 22, 2013
At least one MOS parameter of a MOS fuse is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse is programmed by applying a programming signal to the fuse terminals so that programming current flows through the fuse link. The fuse resistance is mea
8302064 Method of product performance improvement by selective feature sizing of semiconductor devices October 30, 2012
Device features, such as gate lengths and channel widths, are selectively altered by first identifying those devices within a semiconductor die that exhibit physical attributes, e.g., leakage current and threshold voltage magnitude, that are different than previously verified by a de
8302041 Implementation flow for electronic circuit designs using choice networks October 30, 2012
A computer-implemented method of implementing a circuit design that includes an initial network within a programmable logic device can include generating a first choice network from the circuit design according to a first synthesis technique and determining a placement for the first
8301988 Error checking parity and syndrome of a block of data with relocated parity bits October 30, 2012
An apparatus for error checking is described. The apparatus includes a matrix having a plurality of bit position columns and rows, where the bit position columns are equal in number to data bits of a word length, the word length for a word serial transmission of a data vector, where the
8301139 Femtocell configuration using spectrum sensing October 30, 2012
An embodiment of the present invention provides for the ad-hoc configuration of femtocells using spectrum sensing for the selection of spectrum channels. One or more embodiments of the invention determine frequency bands that are not reserved by macrocells in a location, and perform
8299590 Semiconductor assembly having reduced thermal spreading resistance and methods of making same October 30, 2012
Semiconductor assemblies having reduced thermal spreading resistance and methods of making the same are described. In an example, a semiconductor device includes a primary integrated circuit (IC) die and at least one secondary IC die mounted on the primary IC die. A heat extraction eleme
8299564 Diffusion regions having different depths October 30, 2012
Formation of transistors, such as, e.g., PMOS transistors, with diffusion regions having different depths for equalization of performance among transistors of an integrated circuit is described. Shallow-trench isolation structures are formed in a substrate formed at least in part of
8296710 Soft constraints in scheduling October 23, 2012
A method for implementing soft constraints in scheduling comprises receiving a description of circuit behavior. The description is un-timed. A scheduling solution is generated for use in scheduling the description. The scheduling solution includes scheduling variables and an objective
8296690 Method and arrangement providing for implementation granularity using implementation sets October 23, 2012
A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy
8296689 Customizing metal pattern density in die-stacking applications October 23, 2012
Method, apparatus, and computer readable medium for designing an integrated circuit (IC) are described. In some examples, layout data describing conductive layers of the integrated circuit is obtained. The layout data is analyzed to identify through die via (TDV) areas. A metal fill
8296604 Method of and circuit for providing temporal redundancy for a hardware circuit October 23, 2012
A method and circuit for providing temporal redundancy for a hardware circuit implemented in an integrated circuit is disclosed. The method comprises implementing a comparison circuit for comparing values in the integrated circuit; coupling an input signal to the hardware circuit; de
8296578 Method and apparatus for communicating data between stacked integrated circuits October 23, 2012
Method and apparatus for communicating data between vertically stacked integrated circuits is described. In some examples, a method of configuring an integrated circuit which is a first die includes obtaining configuration data at configuration resources of the integrated circuit fro
8296557 Providing multiple selectable configuration sources for programmable integrated circuits with fa October 23, 2012
Within a system comprising a programmable integrated circuit (IC), a method can include storing a first configuration within the system in a read-only memory that is independent of the programmable IC. The programmable IC, being loaded with the first configuration, comprises a circui
8295099 Dual port memory with write assist October 23, 2012
A data value is read from one port of a dual-port memory cell during a clock cycle. A WRITE assist pulse having a delay from an end-of-read signal is generated. The delay and duration of the WRITE assist pulse are optionally user-selectable. A high voltage (e.g., Vdd) is coupled to the
8294490 Integrated circuit and method of asynchronously routing data in an integrated circuit October 23, 2012
An integrated circuit enabling asynchronous data communication is disclosed. The integrated circuit comprises a plurality of circuit blocks, each circuit block of the plurality of circuit blocks comprising programmable resources; and a routing network coupled to each circuit block of
8293547 Hybrid integrated circuit device October 23, 2012
An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is
8286113 Verification of logic core implementation October 9, 2012
A system and method are provided for verifying implementation of a logic core in a complete bitstream. A logic core bitstream is extracted from the complete bitstream. The logic core bitstream is compared to a reference bitstream of the logic core for a target device. In response to
8285944 Read-write control of a FIFO memory with packet discard October 9, 2012
A write controller controls writing of packet data to a memory, and a read controller controls reading of packet data from the memory. The write controller signals the read controller if a packet is to be discarded. In response to a discard signal from the write controller, the read
8285770 Method of and circuit for generating parameters for a predistortion circuit in an integrated cir October 9, 2012
A method of generating parameters for a predistortion circuit in an integrated circuit using a matrix is disclosed. The method comprises storing a first column of a first matrix; generating the remaining columns of the first matrix based upon the first column of the matrix; generatin
8284801 Method and apparatus for controlling an operating mode for an embedded Ethernet media access con October 9, 2012
Method and apparatus for controlling an operating mode of an Ethernet media access controller (MAC) embedded in a programmable device is described. In some examples, a configuration circuit is configured to receive a configuration signal from configuration memory of the programmable
8284772 Method for scheduling a network packet processor October 9, 2012
A method is provided for scheduling a network packet processor. A textual language specification is input of the processing of network packets by the network packet processor. The textual language specification includes memory read actions and modification actions. Each memory read actio
8275047 Method and device for block-based conditional motion compensation September 25, 2012
Methods and devices for encoding and decoding video data are provided, wherein an image data structure can be represented as a group of macroblocks and each macroblock contains a plurality of blocks. One inventive aspect includes a method of decoding image data comprises decoding a c
8271915 One-pass method for implementing a flexible testbench September 18, 2012
A test environment for performing verification on a parameterizable circuit design can include a test harness specifying a first instance of a device under test characterized by a first parameterization and at least a second instance of the device under test characterized by at least
8271911 Programmable hardware event reporting September 18, 2012
Approaches for reporting hardware events from circuitry implemented in an integrated circuit (IC). The IC is configured with a circuit to be analyzed and an event monitor circuit. A process invokes an application programming interface (API) function that references an operating system
8271557 Configuration of a large-scale reconfigurable computing arrangement using a virtual file system September 18, 2012
A top-level directory of a virtual file system is created. A hierarchy of directories is created under the top-level directory including creating a first file that contains an architecture description of the multi-device circuit arrangement. The directories have names indicative of the
8270742 Data compression for computer-aided design systems September 18, 2012
A method of compressing data can include forming at least one container by grouping calls of data according to at least one data element of each call. The method can include arranging, via the processor, calls of the at least one container into a plurality of segments according to a
8270335 Arbitration for time division multiple access using delta sigma modulation September 18, 2012
Method and device for arbitration for time division multiple access using delta-sigma modulation for an integrated circuit are described. A method for arbitrating access to a shared resource among multiple devices includes obtaining a first arbitration factor. The first arbitration f
8270235 Dynamic detection of a strobe signal within an integrated circuit September 18, 2012
A method of processing a strobe signal can include oversampling a strobe signal received from a source synchronous device and determining an amount of time between sending a read request to the source synchronous device and detecting a first pulse of the strobe signal according to the
8269566 Tunable resonant circuit in an integrated circuit September 18, 2012
A tunable resonant circuit includes first and second capacitors that provide a matched capacitance between first and second electrodes of the first and second capacitors. A deep-well arrangement includes a first well disposed within a second well in a substrate. The first and second
8269519 Methods and apparatus for testing of integrated circuits September 18, 2012
Methods and apparatus for testing packaged ICs are disclosed. In some embodiments, an apparatus for testing a packaged integrated circuit (IC) can include a device handler for moving the packaged IC; a testing station for testing the packaged IC; and a pre-test conditioning station c
8269518 Method and apparatus for preventing probe card oxidation September 18, 2012
A method and apparatus for a pre-biasing storage mechanism to prevent oxidation and other contaminants from forming on the probe tips and probe tails of a probe card. The pre-biasing storage mechanism imposes a positive bias on the probe needles of the probe card so as to create phys
8269516 High-speed contactor interconnect with circuitry September 18, 2012
Disclosed is a contactor interconnect in an integrated circuit device test fixture comprises a plurality of contactor pins enabled to provide electrical contact with the contact points of an integrated circuit device, the contactor pins being mounted in the test fixture; and an elect
8266583 Flexible packet data storage for diverse packet processing applications September 11, 2012
A computer-implemented method of developing a packet processing application can include receiving a user input specifying a first function and a second function and automatically generating a high level programming language description of the packet processing application including a
8266553 System and method for detecting mask data handling errors September 11, 2012
An integrated circuit device layout and a method for detecting mask data handling errors are disclosed in which integrated circuit device layout includes a device region in which operable circuitry is disposed. Integrated circuit device layout also includes a verification region in w
8265918 Simulation and emulation of a circuit design September 11, 2012
Co-simulation platforms generally include a software-based system and a hardware-based system in which different portions of the circuit design are either simulated in a software-based system or emulated on a hardware-based system. Before a model of circuit design can be co-simulated
8265917 Co-simulation synchronization interface for IC modeling September 11, 2012
A high-level integrated circuit ("IC") modeling system (400) includes a first co-simulator (418) modeling a first portion of an IC system and a second co-simulator (419) modeling a second portion of the IC system, each co-simulator operating according to initial simulation operating

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