| Patent Number |
Title Of Patent |
Date Issued |
| 7625805 |
Passivation of deep isolating separating trenches with sunk covering layers |
December 1, 2009 |
| Trenches are formed in an SOI wafer to isolate low-voltage and high-voltage elements in the wafer. The isolation trenches are formed with trench coverings that do not protrude above the trenches. Vertical in-trench and horizontal out-of-trench isolation layers are formed and the tren |
| 7598098 |
Monitoring the reduction in thickness as material is removed from a wafer composite and test str |
October 6, 2009 |
| The aim of the invention is to create a simple monitoring or testing method for monitoring a reduction in thickness as material is removed from a bonded semiconductor wafer pair, which prevents failure effects as material is removed from wafers (polishing, grinding or lapping). In ad |
| 7588948 |
Test structure for electrically verifying the depths of trench-etching in an SOI wafer, and asso |
September 15, 2009 |
| The invention provides a simple to implement and reliable recognition of the moment at which insulation trenches reach the buried insulating layer during an etch process. The technological reliability during the etching of such trenches is increased, the production of refuse is prevented |
| 7535074 |
Monolithically integrated vertical pin photodiode used in biCMOS technology |
May 19, 2009 |
| The invention relates to a monolithically integrated vertical pin photodiode which is produced according to BiCMOS technology and comprises a planar surface facing the light and a rear face and anode connections located across p areas on a top face of the photodiode. An i-zone of the |
| 7520161 |
Tightness test for disk bond connections and test structure for carrying out said method |
April 21, 2009 |
| A process and a test structure for testing the hermeticity of bond connections are described. Points are provided on the wafer pair to be connected, at which hermetically closed cavities are additionally formed upon the connection of the wafers, e.g., as they are customary in microel |
| 7517813 |
Two-step oxidation process for semiconductor wafers |
April 14, 2009 |
| An efficient method for the thermal oxidation of preferably silicon semiconductor wafers using LOCOS (local oxidation of silicon) processes is described. The mechanical stresses of the wafers are to be reduced. To this end, an oxidation method is proposed that comprises providing a s |
| 7509875 |
Electrical determination of the connection quality of a bonded wafer connection |
March 31, 2009 |
| The invention relates to a method and arrangement for carrying out the nondestructive determination of the connection quality of bonded wafers (1, 8) in order to verify the connection strength. The fact that an unbonded region (9) forms around a raised or recessed structure (3) on at |
| 7491925 |
Photodetector comprising a monolithically integrated transimpedance amplifier and evaluation ele |
February 17, 2009 |
| The aim of the invention is to configure a photodetector (10) such that no disadvantages are created for processing low luminous intensities on detectors known in prior art, especially when monolithically integrating the evaluation electronics. Said aim is achieved by a photodetector for |
| 7485926 |
SOI contact structures |
February 3, 2009 |
| Disclosed are an arrangement and a production method for electrically connecting active semiconductor structures in or on a monocrystalline silicon layer (12) located on the front face (V) of silicon-on-insulator semiconductor wafers (SOI, 10) to the substrate (13). The electrical co |
| 7349070 |
Multiple level photolithography |
March 25, 2008 |
| A method is provided for performing photolithography on a substrate which has a first region on a lower level and a second region on an upper level, wherein a first pattern area exists within said first region, a second pattern area exists within said second region, and at least said |
| 7271074 |
Trench insulation in substrate disks comprising logic semiconductors and power semiconductors |
September 18, 2007 |
| Disclosed is a layer arrangement (4b, 5b, 9b, 10, 9a, 5a, 4a) within an insulating trench, which insulates circuits with little distortion while being suitable for electrically insulating high-voltage power components (7) relative to low-voltage logic elements (6) that are integrated on |
| 7195961 |
SOI structure comprising substrate contacts on both sides of the box, and method for the product |
March 27, 2007 |
| Disclosed are an arrangement and a production method for electrically connecting (20) active semiconductor structures (40) in the monocrystalline silicon layer (12) located on the front face of silicon-on-insulator semiconductor wafers (SOI; 10) to the substrate (13) located on the r |
| 6622101 |
Quality surveillance of a production process |
September 16, 2003 |
| Method for monitoring a quality of a plurality of particularly different technical product types which are produced in a quasi-parallel manufacturing process, the manufacturing method including several sequentially arranged manufacturing stations, and whereby a course of a state vari |
