| Patent Number |
Title Of Patent |
Date Issued |
| 7631136 |
State negotiation method in PCI-E architecture |
December 8, 2009 |
| In a state negotiation method of a PCI-E upstream device supporting multiple downstream configurations, a state of a second link asserted by a second state machine of the PCI-E upstream device is detected when a first link asserted by a first state machine of the PCI-E upstream device |
| 7630647 |
Hybrid IR transmission system |
December 8, 2009 |
| A hybrid IR transmission system implements at least two IR transmission protocols with a common IR transceiver. The hybrid IR transmission system includes an IR decoding circuit, a common IR transceiver and a filter circuit. The IR decoding circuit includes an IrDA module for decoding IR |
| 7629980 |
Color-revealing method, color-changing method and color-processing device |
December 8, 2009 |
| A method is used for changing colors of a first image frame to form a second image frame. Palette index values of the first image frame are first read. Then, color change index values specific to the second image frame and correlating to the palette index values are read respectively |
| 7626905 |
Method and device for protecting a slicer in reading signals on a defect disc |
December 1, 2009 |
| A device for protecting a slicer in reading signals on a defect disc from disturbance and instability is provided. The device includes a defect detection unit, a slicer and a logic combination unit. The defect detection unit receives a plurality of defect detection signals to detect |
| 7626521 |
Decoding control of computational core of programmable graphics processing unit |
December 1, 2009 |
| Various embodiments of decoding systems and methods are disclosed. One method embodiment, among others, comprises providing a shader configurable with a plurality of instruction sets to decode a video stream coded a plurality of different coding methods, loading the shader having one |
| 7626518 |
Decoding systems and methods in computational core of programmable graphics processing unit |
December 1, 2009 |
| Various embodiments of decoding systems and methods are disclosed. One system embodiment, among others, comprises a software programmable core processing unit having a variable length decoding unit (VLD) unit configured to execute a shader, the shader configured to selectively implem |
| 7626480 |
Spiral inductor with multi-trace structure |
December 1, 2009 |
| A spiral inductor with a multi-trace structure having an insulating layer disposed on a substrate. A first spiral conductive trace with multiple turns is disposed on the insulating layer, wherein the outermost turn and the innermost turn of the first spiral conductive trace have a first |
| 7624286 |
Power management method of north bridge |
November 24, 2009 |
| A power state management method of north bridge. The north bridge monitors power transition state of processor; then adjusting operating clocks and operating voltage of the processor and the main memory according to the determined power state to saving power consumption. |
| 7623481 |
Hyper throughput method for wireless local area network |
November 24, 2009 |
| A hyper throughput packet transmission method for a wireless local area network operating in burst and protection mode is provided. A first CTS frame is sent, comprising an NAV to reserve the medium for a duration. Upon completion of the first CTS frame delivery, a plurality of data |
| 7623049 |
Decoding of context adaptive variable length codes in computational core of programmable graphic |
November 24, 2009 |
| Various embodiments of decoding systems and methods are disclosed. One system embodiment, among others, comprises a software programmable core processing unit having a context-adaptive variable length coding (CAVLC) unit configured to execute a shader, the shader configured to implement |
| 7622326 |
Manufacturing process of a chip package structure |
November 24, 2009 |
| A manufacturing process of a chip package structure is provided. The manufacturing method uses fine pitch circuit processes, such as a TFT-LCD process or an IC process, to increase layout density and shorten electrical transmission pathways so that a higher electrical performance lev |
| 7620826 |
Thermal throttling duty estimation methods and systems for a CPU |
November 17, 2009 |
| Thermal throttling duty estimation methods for a CPU (Central Processing Unit) in a computer system are provided. The temperature of a CPU is highly related to the CPU performance. CPU temperature data (CPUT) is first acquired. A thermal throttle duty (TTD) is then calculated accordi |
| 7616722 |
Method and circuitry for extracting clock in clock data recovery system |
November 10, 2009 |
| A method for extracting a clock in a clock data recovery system is provided. The method includes the following steps. First, a serial link transmission data is sampled for a plurality of times, and a plurality of pulse signals are generated and sequentially arranged. Then, a mark is |
| 7615708 |
Arrangement of non-signal through vias and wiring board applying the same |
November 10, 2009 |
| An arrangement of non-signal through vias suitable for a wiring board is provided. The wiring board has a contact surface, a core layer and pads. The contact pads are disposed on the contact surface, while the arrangement of non-signal through vias includes first non-signal through v |
| 7613959 |
Data receiving apparatus of a PCI express device |
November 3, 2009 |
| A data receiving apparatus of a PCI Express system includes a receiving device, an 8B10B decoder, a forged packet removing device, and a descrambling circuit. The forged packet removing device determines whether a disparity error occurs; and an offset removing circuit compensates a n |
| 7613089 |
Monitor and adjust method for optical disc recording |
November 3, 2009 |
| A method is disclosed for adjusting write power when recording an optical disc. First, pre-setting a range of a write quality parameter and a write power. Next, moving a spindle motor and an optical pickup head to a target track. After the spindle motor is stable at the intended rotation |
| 7610513 |
Debug device for detecting bus transmission and method thereof |
October 27, 2009 |
| This invention relates to a debug device and method thereof and is applied to detect transmission on a bus in a computer system having a CPU, a north bridge chip and a south bridge chip. The debug device consists of a processing unit, a comparing unit and a recording unit. The processing |
| 7610497 |
Power management system with a bridge logic having analyzers for monitoring data quantity to mod |
October 27, 2009 |
| A core logic coupled to a main memory of a computer, comprising an analyzer and a power management unit. The analyzer monitors access request traffic load of main memory. The power management unit employs various power performance trade-off activities with the knowledge of the monito |
| 7610465 |
Method and related apparatus for data migration utilizing disk arrays |
October 27, 2009 |
| Method and related apparatus for data migration of a disk array. While striping and migrating data of a source disk of the disk array, data stripes are grouped into different zones; after completely writing data stripes of a given zone to disks of the disk array, data stripes of next |
| 7610454 |
Address decoding method and related apparatus by comparing mutually exclusive bit-patterns of ad |
October 27, 2009 |
| A memory address decoding method for determining if a given address is located in one of a plurality of sections. Each section has a plurality of memory units and each memory unit has a unique corresponding address, the corresponding address using the binary system. The method includes |
| 7609795 |
Interpolation module, interpolator and methods capable of recovering timing in a timing recovery |
October 27, 2009 |
| The invention relates to an interpolation module, an interpolator, and methods capable of recovering timing, and in particular, to an interpolation module, an interpolator, and methods capable of recovering timing in a timing recovery apparatus. An interpolation module capable of rec |
| 7609770 |
Circuit structure and signal encoding method for a serial ATA external physical layer |
October 27, 2009 |
| A circuit structure and signal encoding method for a serial ATA external physical layer is provided. The circuit structure and signal encoding method thereof is capable of reducing the number of interface signals of a serial ATA external physical layer, essentially comprising a decod |
| 7609108 |
Phase-locked loop and compound MOS capacitor thereof |
October 27, 2009 |
| Compound MOS capacitors and phase-locked loop with the compound MOS capacitors are disclosed. In the phase-locked loop, the compound MOS capacitors of the loop filter are HV (high voltage) devices, and the voltage control oscillator is a LV (low voltage) device. The compound MOS capa |
| 7608923 |
Electronic device with flexible heat spreader |
October 27, 2009 |
| A package module is provided. The package module includes a substrate having a surface including a die region. A die is disposed in the die region of the surface on the substrate. A flexible heat spreader conformally covers the surface of the substrate and the die. The invention also |
| 7607029 |
PCI express link state management system and method thereof |
October 20, 2009 |
| A PCI Express link state management system and method thereof is disclosed. The PCI Express link power state management system includes an upstream device, a downstream device and a link. First, the upstream device outputs a configuration request to the downstream device so as to cha |
| 7602975 |
Method and apparatus for image compression |
October 13, 2009 |
| A method and an apparatus for image compression. First, an image is partitioned into a plurality of image blocks, the image having A.times.B pixels, each of the image blocks having N.times.M pixels, wherein N is less than A and M is less than B. Next, a selected image block is output |
| 7602402 |
Method of displaying colors of graphic objects on screen control display |
October 13, 2009 |
| A method of displaying color objects for the screen control display is provided. First, a plurality of elements and son elements on a screen control display respectively to a first level list and a plurality of second level lists is provided. Each of said elements of said first level |
| 7600074 |
Controller of redundant arrays of independent disks and operation method thereof |
October 6, 2009 |
| A controller and operation method for RAID (Redundant Array of Independent Disks) is provided. The controller includes a receiving module, a splitting module, a sorting module and a transceiver. And the operation method includes the following steps. First, at least one read/write com |
| 7600067 |
Methods for identifying bridge devices and systems thereof |
October 6, 2009 |
| Methods for identifying bridge devices and systems thereof. A bridge device receives a standard command. In response to the standard command, output information comprising at least one no-available parameter is generated. The bridge device sets the no-available parameter in the outpu |
| 7600066 |
Methods for identifying bridge devices and systems thereof |
October 6, 2009 |
| Methods for identifying bridge devices and systems thereof. A bridge device receives an undefined command. In response to the undefined command, output information comprising at least one no-available parameter is generated. The bridge device sets the no-available parameter as a pred |
| 7599382 |
Serial transceiver and method of transmitting package |
October 6, 2009 |
| A serial transceiver transmits at least one package of a data link layer and includes at least one channel including at least one transmitting module and at least one receiving module, a generating module and a controlling module. The channel is for transmitting the corresponding pac |
| 7599325 |
Method and circuit for reducing power consumption of a wireless local network |
October 6, 2009 |
| A method for reducing power consumption of a wireless local area network is provided. The wireless local area network comprises a first station communicating according to a first version communication standard, a second station communicating according to a second version communication |
| 7598836 |
Multilayer winding inductor |
October 6, 2009 |
| A multilayer winding inductor. The inductor at least includes multi-level interconnect and single-level interconnect structures. The multi-level interconnect structure includes a plurality of conductive plugs and a plurality of looped conductive traces overlapping and separated from each |
| 7598592 |
Capacitor structure for integrated circuit |
October 6, 2009 |
| A capacitor structure for an integrated circuit. An insulating layer is disposed on a substrate. A first conductive line is embedded in a first level of the insulating layer. A second conductive line is embedded in a second level of the insulating layer lower than the first level and has |
| 7596155 |
Method and apparatus for packet error detection |
September 29, 2009 |
| The invention provides a packet error detecting method for a PCI express bus link. When a start framing symbol of a packet appears at the PCI express bus link, the start framing symbol is ignore if a predetermined error condition is satisfied. |
| 7596047 |
Memory card and control chip capable of supporting various voltage supplies and method of suppor |
September 29, 2009 |
| A memory card and a control chip capable of supporting various voltage supplies and a method of supporting voltages are discussed. The memory card includes a flash memory and a control chip for controlling the flash memory, and the control chip has a voltage regulator, a pad power su |
| 7594058 |
Chipset supporting a peripheral component interconnection express (PCI-E) architecture |
September 22, 2009 |
| The present computing system using PCI-E architecture includes at least one first PCI-E port, a first port-arbiter, a first URD logic, a microprocessor, a DARD logic and a device arbiter. The first port-arbiter receives a data from the first PCI-E port. The first URD logic is coupled |
| 7590876 |
Method for adjusting a frequency working between a north bridge chip and a random access memory |
September 15, 2009 |
| A frequency working between the north bridge chip and random access memory of a computer system is dynamically and automatically adjusted in response to the frequency change of the CPU, in response to the workload of the north bridge chip or in response to the change of settings in a |
| 7590790 |
Bus device |
September 15, 2009 |
| A bus device is used with a computer system. In the bus device, a bus-interfaced host performs data transmission in a first mode in response to a first command resulting from certain software execution of the computer system. A bridge device is coupled to and communicable with the bu |
| 7590787 |
Apparatus and method for ordering transaction beats in a data transfer |
September 15, 2009 |
| A microprocessor including a cache memory and bus interface logic. The bus interface logic is interfaced with request signals and data signals and includes a request interface and a response interface. The request interface provides a request via the request signals for a data transa |
| 7589597 |
Ultra wideband and fast hopping frequency synthesizer for MB-OFDM wireless application |
September 15, 2009 |
| A frequency synthesizer with a single PLL and multiple SSB mixers is presented. The frequency synthesizer includes a single PLL outputting a reference signal that is fed to a plurality of dividers coupled in sequence. The outputs from the dividers are mixed by the SSB mixers to produ |
| 7587651 |
Method and related apparatus for calibrating signal driving parameters between chips |
September 8, 2009 |
| A calibrating method for adjusting related parameters when a first chip and a second chip switch signals is disclosed. The calibrating method includes: utilizing the first chip to output a test signal through using a first driving force in order to represent a test value; utilizing the |
| 7586320 |
Plunger and chip-testing module applying the same |
September 8, 2009 |
| A plunger is suitable for a chip-testing module having a probe card, which has a circuit board and a membrane. The membrane has a circuit layer disposed on a first membrane surface of the membrane, conductive through-vias penetrating the membrane, and bumps disposed on a second membr |
| 7586188 |
Chip package and coreless package substrate thereof |
September 8, 2009 |
| A chip package includes a coreless package substrate and a chip. The coreless package substrate includes an interconnection structure and a ceramic stiffener. The interconnection structure has a first inner circuit, a carrying surface and a corresponding contact surface. The first in |
| 7583549 |
Memory output circuit and method thereof |
September 1, 2009 |
| An output circuit of a memory is provided. The output circuit includes a first pre-charge circuit, a multiplexer, and a sense amplifier. The first pre-charge circuit pre-charges the voltage of a target readout bit line to the logic high level according to a pre-charge signal. The multipl |
| 7583268 |
Graphics pipeline precise interrupt method and apparatus |
September 1, 2009 |
| A graphics processing unit ("GPU") is configured to interrupt processing of a first context and to initiate processing of a second context upon command. A command processor communicates an interrupt signal on a communication path from to a plurality of pipeline processing blocks in a |
| 7581072 |
Method and device for data buffering |
August 25, 2009 |
| A data buffer device that includes a write unit and a read unit, and is disposed between a first interface device and a second interface device is provided. The write unit further includes a first write buffer, a second write buffer and a write controller. The write controller controls |
| 7580498 |
Closed loop control system and method of dynamically changing the loop bandwidth |
August 25, 2009 |
| The invention provides a method for dynamically changing the loop bandwidth of a closed loop control system. At least one loop bandwidth parameter controls the loop bandwidth of the closed loop control system. An error signal reflecting the convergence status of the output signal of |
| 7580357 |
Method for implementing varying grades of service quality in a network switch |
August 25, 2009 |
| The invention provides a method for implementing varying service quality grades in a network switch. First, a plurality of users of the network switch is classified into a plurality of service quality grades according to a contributing factor of the plurality of the users. Each of the |
| 7580309 |
Memory refresh method and system |
August 25, 2009 |
| A memory refresh method applicable in a system memory is disclosed. The memory system comprises a plurality of memory ranks. It is to determine whether an access request corresponds to the memory rank, and an idle auto-refresh number of the memory rank is calculated if there is no ac |
