Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Verigy Patents
Assignee:
Verigy
Address:
Singapore) Pte. Ltd. (Singapore, SG
No. of patents:
69
Patents:


1 2


Patent Number Title Of Patent Date Issued
7617503 Method and apparatus for determining which of two computer processes should perform a function X November 10, 2009
In one embodiment, a method for determining which of two computer processes should perform a function X includes the following actions. If a second computer process is dependent on data received at a first computer process, it is determined whether the second computer process current
7614286 Methods for sampling equipment and fluid conditions November 10, 2009
In one embodiment, a sampling device is connected to equipment having a fluid flow path. The sampling device has a chamber that defines a fluid flow path, and has a tubular sampling coupon that is positioned within the chamber. The tubular sampling coupon further defines the fluid flow
7590903 Re-configurable architecture for automated test equipment September 15, 2009
An adaptive test system includes one or more reconfigurable test boards, with each test board including at least one re-configurable test processor. The re-configurable test processors can transmit communicate with one another using an inter-processor communications controller associ
7587015 Asynchronous digital data capture September 8, 2009
The present invention provides asynchronous digital capture by first, capturing the digital output of the device under test (DUT) clock on an automated test equipment (ATE) digital channel. Next, the NRZ output data of the DUT is captured while the clock signal is captured on adjacent AT
7584395 Systems, methods and apparatus for synthesizing state events for a test data stream September 1, 2009
In one embodiment, a method of has the steps of A) accessing a stream of test data comprising 1) a number of state events and 2) a number of data events interspersed with the ones of the state events; B) upon accessing one of the data events, determining if the data event is in conformit
7581148 System, method and apparatus for completing the generation of test records after an abort event August 25, 2009
A system for formatting test data includes at least one data formatter to retrieve test data from a data store, upon receiving notifications of test events, and to generate a number of test records based on the test data. The system further includes an abort handler to cause at least one
7574185 Method and apparatus for generating a phase-locked output signal August 11, 2009
A method and apparatus for generating a phase-locked output signal includes generating an intermediate signal phase locked to an input signal by frequency dividing the intermediate signal by a temporally-varying divide ratio sequence to generate a first feedback signal and phase comp
7555639 Method for configuring a data formatting process using configuration values of a highest priorit June 30, 2009
In one embodiment, one or more data structures that define associations between a plurality of configuration keys and a plurality of configuration values are accessed, and a highest priority configuration value is retrieved for each of the plurality of configuration keys. The configu
7552530 Method of manufacturing a PCB having improved cooling June 30, 2009
An improved cooling of an electronic component loaded to a printed circuit board, wherein the PCB comprises at its upper side at least one electronic component, and at least one heat conducting member inserted into a through-hole of the PCB, wherein the HCM extends from the upper sid
7550988 Test device with test parameter adaptation June 23, 2009
A test device for testing a device under test, wherein the test device is adapted for providing a connection to a central controller, the test device comprising a first interface for receiving a test procedure activation signal from the central controller, and a processor for perform
7541824 Forced air cooling of components on a probecard June 2, 2009
A probe card with an air channel over the active components for cooling the active components on the probe card is provided.
7536663 Method and apparatus for quantifying the timing error induced by an impedance variation of a sig May 19, 2009
In one embodiment, a plurality of signals are sequentially driven onto a signal path. Each of the signals has a pulsewidth defined by a trigger edge and a sensor edge, and at least some of the signals having different pulsewidths. After driving each signal, the signal is sampled at or ab
7519887 Apparatus for storing and formatting data April 14, 2009
In one embodiment, apparatus includes a data populator that is provided to 1) receive a plurality of events, 2) create a plurality of data objects in memory, with at least some of the data objects corresponding to logical groupings of data implied by ones of the events, 3) relate data
7519827 Provisioning and use of security tokens to enable automated test equipment April 14, 2009
Automated test equipment (ATE) is provided with a plurality of hardware components, at least two of which provide a common test feature. The ATE is also provided with program code to access a number of security tokens, each token of which grants rights to use one or more test features
7518454 Operational amplifier selecting one of inputs, and an amplifying apparatus using the OP amplifie April 14, 2009
A current feedback-type operational amplifier comprising multiple input parts and one output part, wherein each of the multiple input parts comprises a first input terminal, a second input terminal, and an output terminal, the signals input from the first input terminal are buffer am
7512858 Method and system for per-pin clock synthesis of an electronic device under test March 31, 2009
A method and system for synthesizing digital clock signals for an electronic device under test having a plurality of pins, said method including generating centrally a reference clock, and distributing said reference clock to a number of electronic circuits, each of said electronic c
7502974 Method and apparatus for determining which timing sets to pre-load into the pin electronics of a March 10, 2009
In one embodiment, a method includes, providing a test program designed to control a circuit test system. The circuit test system has a plurality of test channels, each test channel of which is configured to be selectively coupled to a plurality of sub-channels under control of the test
7501844 Liquid cooled DUT card interface for wafer sort probing March 10, 2009
A water block heat dissipation on a probe card interface for cooling active components and other devices requiring heat dissipation on the probe card is presented.
7482817 Method and an apparatus for measuring the input threshold level of device under test January 27, 2009
A signal including at least one group of a group comprised of two slopes having different gradients and a known temporal position relationship is applied to a device under test, the time intervals between the specific transitions of the logic level produced in the output signal of the
7480583 Methods and apparatus for testing a circuit January 20, 2009
In one embodiment, when a test program for testing a circuit specifies the application of a DC voltage to a particular node of the circuit, i) an operational amplifier of a circuit test system is configured to respond to remote feedback, wherein the remote feedback is responsive to a loa
7459921 Method and apparatus for a paddle board probe card December 2, 2008
A paddle board probe card for connecting a device under test with an ATE tester by means of ZIF connectors is presented. The paddle board probe card may include more than one printed circuit board mounted on a probe card in such a manner that the more than one printed circuit boards mate
7457729 Model based testing for electronic devices November 25, 2008
The model-based method tests compliance of production devices with the performance specifications of a device design. The production devices are manufactured in accordance with the device design by a manufacturing process. In the method, a simple model form based on the device design
7452214 Interconnect assemblies, and methods of forming interconnects, between conductive contact bumps November 18, 2008
In one embodiment, an interconnect assembly includes conductive contact bumps extending from a bumped flex circuit assembly, and conductive contact pads attached to a rigid printed circuit assembly. Each conductive contact pad has a contact surface having a hole and an abutment zone
7444566 Memory device fail summary data reduction for improved redundancy analysis October 28, 2008
A method and apparatus is presented for extracting sparse failure information from an error data image of a memory device by scanning the error data image in only two passes. During a first scan pass, the error data image is scanned for failures in a first set of memory cell groups o
7434118 Parameterized signal conditioning October 7, 2008
A coupling unit is adapted to be coupled between a first and a second unit to be tested. Said coupling unit comprises a first signal path that is adapted to provide a signal connection between at least one terminal of the first unit to be tested and at least one terminal of the second un
7421632 Mapping logic for controlling loading of the select ram of an error data crossbar multiplexer September 2, 2008
Methods and circuits for efficient configuration an error data crossover configuration circuit of an integrated circuit tester allows simultaneous DUT channel configuration for multiple identical DUTs for an error data control circuit.
7421360 Method and apparatus for handling a user-defined event that is generated during test of a device September 2, 2008
In one embodiment, and in response to an ordered sequence of events corresponding to execution of a plurality of tests on at least one device under test (DUT), 1) a plurality of data objects are created, the data objects including A) some data objects that correspond to logical group
7420385 System-on-a-chip pipeline tester and method September 2, 2008
A pipeline tester is disclosed that is capable of testing systems-on-a-chip (SOCs) or Devices Under Test (DUTs) in pipeline fashion. The tester provides faster, more economical testing of such SOCs and DUTs, which are loaded sequentially into the tester. A plurality of underlying tes
7415479 Method and apparatus for assigning test numbers August 19, 2008
In a method for assigning test numbers, current testflow context information is maintained during execution of a testflow. Upon execution of a subtest in the testflow, a database of test numbers is indexed using index information comprising 1) an identifier of the subtest, and 2) the
7414558 Digital to analog conversion using summation of multiple DACs August 19, 2008
A method for converting a digital signal to an analog signal, said method including a plurality of signal sources, preferably current sources, one or more of said signal sources being variable output signal magnitude sources, said method including the steps of setting the output signal
7412639 System and method for testing circuitry on a wafer August 12, 2008
A system and method in which a plurality of dice on a semiconductor wafer are interconnected to enable efficient testing thereof. In certain embodiments a plurality of dice are interconnected in a manner that enables test data to be communicated from a tester system to a plurality of
7404121 Method and machine-readable media for inferring relationships between test results July 22, 2008
In one embodiment, a method for inferring relationships between test results receives sequential test data from a tester performing tests on a number of devices under test (DUTs); upon receiving a DUT identifier, determines if a data structure exists for the DUT identified by the one
7404109 Systems and methods for adaptively compressing test data July 22, 2008
Systems and methods for adaptively compressing test data are disclosed. One such method comprises the steps of examining a test data file that includes a first plurality of data units corresponding to a first plurality of DUT pins and a second plurality of data units corresponding to
7403874 Method and system for prioritizing formatting actions of a number of data formatters July 22, 2008
In one embodiment, a method of prioritizing formatting actions of a number of data formatters 1) instantiates a number of threads for execution by a processing system, the number of threads sharing thread processing resources, and the number of threads including at least two threads of
7397235 Pin electronic for automatic testing of integrated circuits July 8, 2008
A pin electronic adapted for use in an automatic test equipment for testing integrated circuits ICs includes a driver circuit having an input for receiving an input signal from a data source and an output connected with an input pin of a device under test, and a feedback circuit having
7386777 Systems and methods for processing automatically generated test patterns June 10, 2008
Representative embodiments are generally directed to storing compressed test pattern data on an automated test equipment (ATE) device. In one embodiment, the test pattern data is compressed according to a linear feedback shift register (LFSR). The LFSR may possess a low probability of
7379856 Modeling an electronic device May 27, 2008
For modeling a first device, a measured electrical behavior in at least one of time and frequency domain is received, wherein the measured electrical behavior at least substantially represents at least a portion of the electrical behavior of the first device. The first device is mode
7378862 Method and apparatus for eliminating automated testing equipment index time May 27, 2008
The present invention eliminates the indexing time of an SOC tester, or at least reduces it to the time delay for an electronic switch to toggle or a mechanical shift to occur between two banks of DUTs to be tested on a DUT load board mounted on a test head.
7378860 Wafer test head architecture and method of use May 27, 2008
A wafer test head and ATE for testing semiconductor wafers. The wafer test head having a plurality of sides that can each be used to test a different semiconductor wafer. The architecture of the wafer test head enables electrical connections to probe card located on two different sid
7373360 Methods and apparatus that use contextual test number factors to assign test numbers May 13, 2008
In a method for assigning test numbers, current testflow context information is maintained during the execution of a testflow. If one or more test number factors have been specified for one or more levels of the current testflow context, the test number factors are used to determine
7366937 Fast synchronization of a number of digital clocks April 29, 2008
The present invention relates to a method for synchronizing a number of digital clocks to a synchronizing signal, said method comprising generating centrally a reference clock, synthesizing said digital clocks from said reference clock using a clock multiplier, respectively, resettin
7355378 Source synchronous sampling April 8, 2008
There is provided a method of source synchronous sampling, where a first clock signal of a first unit is synchronized to a second signal received from a second unit. The method includes determining a timing control signal on the base of the first clock signal and the second signal, g
7346102 Channel with domain crossing March 18, 2008
A channel adapted for at least one of providing and receiving signals comprises a channel clock domain, whereby said channel clock domain is under clock control of a channel clock. The channel clock domain comprises at least one of: a drive path adapted for providing signals and a re
7340688 Application of paging to a dataset, graphical display window and graphical scrollbar grip March 4, 2008
A dataset is divided into overlapping logical pages, each associated with a different page index. A graphical display window is then filled with data corresponding to a current page offset which is mapped into a subset of data in a logical page corresponding to a current page index. Even
7339844 Memory device fail summary data reduction for improved redundancy analysis March 4, 2008
A method and apparatus for filtering failures due to must-repair rows or columns from a memory test fail summary image includes current available redundant row failure counts respectively associated with rows of a memory device and current available redundant column failure counts as
7333042 Method and system for digital to analog conversion using multi-purpose current summation February 19, 2008
A method and a corresponding system for converting a digital signal to an analog signal using a plurality of signal sources, preferably current sources, at least two of the signal sources being equal output signal magnitude sources, said method including controlling the equal output
7328137 Methods and systems for derivation of missing data objects from test data February 5, 2008
In an embodiment, there is disclosed a system for derivation of missing data objects from test data. The system may include a data populator having code for: (1) generating data objects from the test data, (2) arranging the data objects in a tree structure, (3) deriving the missing d
7323897 Mock wafer, system calibrated using mock wafer, and method for calibrating automated test equipm January 29, 2008
In one embodiment, a mock wafer for calibrating automated test equipment includes a printed circuit board having a number of interconnect areas, with each interconnect area having a pair of mock die pads that are coupled via a connecting trace. In another embodiment, a method for cal
7321999 Methods and apparatus for programming and operating automated test equipment January 22, 2008
In one embodiment, an electronic device is tested using automated test equipment (ATE) by 1) storing different vectors of scan load data in memory of the ATE; 2) storing a scan unload subroutine in the memory of the ATE; 3) stimulating the electronic device by retrieving the different
7321967 System and method for configuring capabilities of printed circuit boards January 22, 2008
Methods for configuring the capabilities of electronic systems containing printed circuit boards are provided. One such method comprises: providing an initial configuration describing a first set of capabilities corresponding to each PCB as currently configured; modifying the initial
1 2

 
 
  Recently Added Patents
Carbon black surface-modified with benzene compound and carbon black dispersion composition for black matrix using the same
Pocket torch
System and/or method for reading, measuring and/or controlling intensity of light emitted from an LED
Wireless telecommunications system for accessing information from the world wide web by mobile wireless computers through a combination of cellular telecommunications and satellite broadcastin
Method and system for authorizing access to user information in a network
Plasma display panel
System for supplying service from an appliance to multiple consumer electronic devices
  Randomly Featured Patents
Hard disk drive housing for a micro data processor
Use of reactive distillation in the manufacture of methyl tertiary butyl ether
Self-oscillation type signal converter
Detachable volved dispensing head for bottle
Combined digital audio disc player and radio tuner for an automobile
Apparatus and method for transferring operation, administration and management cells across and ATM data frame user network interface
Method and apparatus for generating realistic images using a discrete representation
Intake port of lean burn engine and core thereof
Wound gels
Near object detection system