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Vanguard International Semiconductor Corporation Patents
Assignee:
Vanguard International Semiconductor Corporation
Address:
Hsinchu, TW
No. of patents:
594
Patents:


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Patent Number Title Of Patent Date Issued
8581344 Laterally diffused metal oxide semiconductor transistors November 12, 2013
A laterally diffused metal oxide semiconductor transistor. The laterally diffused metal oxide semiconductor transistor includes a substrate, a drain formed thereon, a source formed on the substrate, comprising a plurality of individual sub-sources respectively corresponding to various
8278736 Electrostatic discharge protection device October 2, 2012
An electrostatic discharge protection device coupled between a first power line and a second power line is provided. A first N-type doped region is formed in a P-type well. A first P-type doped region is formed in the first N-type doped region. A second P-type doped region includes a
8278715 Electrostatic discharge protection device October 2, 2012
An ESD protection structure is disclosed. A substrate comprises a first conductive type. A first diffusion region is formed in the substrate. A first doped region is formed in the first diffusion region. A second doped region is formed in the first diffusion region. A third doped reg
8252652 Semiconductor structure and fabrication method thereof August 28, 2012
A semiconductor structure is provided. A second conductivity type well region is formed on a first conductivity type substrate. A second conductivity type diffused source and second conductivity type diffused drain are formed on the first conductivity type substrate. A gate structure
8237239 Schottky diode device and method for fabricating the same August 7, 2012
A Schottky diode device is provided, including a p-type semiconductor structure. An n drift region is disposed over the p-type semiconductor structure, wherein the n drift region comprises first and second n-type doping regions having different n-type doping concentrations, and the s
8232596 Semiconductor structure and fabrication method thereof July 31, 2012
A method for fabrication of a semiconductor device is provided. A first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the
8211805 Method for forming via July 3, 2012
The invention provides a method for forming a via. A first dielectric layer is formed on a substrate. A conductive structure is formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and conductive structure. A first etching step is pe
8211774 Method for forming semiconductor structure July 3, 2012
The invention provides a method for forming a semiconductor structure. A substrate is provided. A conductive layer is formed on the substrate. A first patterned mask layer is formed on the conductive layer. The conductive layer exposed by the first patterned mask layer is removed to
8154078 Semiconductor structure and fabrication method thereof April 10, 2012
A semiconductor structure is provided. A second conductivity type well region is disposed on a first conductivity type substrate. A gate structure comprising a first sidewall and second sidewall is provided. The first sidewall is disposed on the second conductivity type well region.
8125028 Semiconductor devices for high power application February 28, 2012
Semiconductor devices for high voltage application are presented. A high power semiconductor device includes a first type doped semiconductor substrate and a second type doped epitaxial layer deposited thereon. A first type doped body region is disposed in the second type doped epita
8103995 Method for OPC correction January 24, 2012
An optical proximity correction method is disclosed, comprising establishing an optical proximity correction (OPC) model, and performing an OPC correction step to correct segments of a layout pattern. The OPC correction comprises the step of defining an edge of the layout pattern nei
8093630 Semiconductor device and lateral diffused metal-oxide-semiconductor transistor January 10, 2012
The invention provides a semiconductor device and a lateral diffused metal-oxide-semiconductor transistor. The semiconductor device includes a substrate having a first conductive type. A gate is disposed on the substrate. A source doped region is formed in the substrate, neighboring
8080881 Contact pad supporting structure and integrated circuit for crack suppresion December 20, 2011
The invention provides a contact pad supporting structure. The contact pad supporting structure includes an underlying first conductive plate and an overlying second conductive plate, wherein the first and second conductive plates are separated by a first dielectric layer. A plurality
8080455 Method for fabricating semiconductor device with increased breakdown voltage December 20, 2011
A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is p
8067283 Semiconductor device fabricating method November 29, 2011
A semiconductor device fabricating method is described. The semiconductor device fabricating method includes providing a substrate. A first gate insulating layer and a second gate insulating layer are formed on the substrate, respectively. A gate layer is blanketly formed. A portion of
8063444 Lateral diffused metal oxide semiconductor (LDMOS) devices with electrostatic discharge (ESD) pr November 22, 2011
Lateral diffused metal oxide semiconductor (LDMOS) devices with electrostatic discharge (ESD) protection capability are presented for integrated circuits. The LDMOS device includes a semiconductor substrate with an epi-layer thereon. Patterned isolations are disposed on the epi-layer
8063439 Semiconductor device and fabrication method thereof November 22, 2011
A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the
8058121 Method for fabricating semiconductor device, method for fabricating bipolar-CMOS-DMOS November 15, 2011
A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type fro
8049307 Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices November 1, 2011
Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active r
8008726 Trig modulation electrostatic discharge (ESD) protection devices August 30, 2011
Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region a
8008687 Electrostatic discharge protection device August 30, 2011
An electrostatic discharge protection device including a substrate, a first doped region, a first gate electrode, a second doped region, a second gate electrode, and a third doped region is disclosed. The substrate has a first conductive type. The first doped region has a second cond
8008212 Fabrication methods for integration CMOS and BJT devices August 30, 2011
Fabrication methods for integrating CMOS and BJT devices are presented. A semiconductor substrate having a first region and a second region are provided, wherein the first region includes a CMOS device, and the second region includes a BJT device. A dielectric layer is conformably deposi
7929328 Memory and storage device utilizing the same April 19, 2011
A storage device including a memory and a reading circuit is disclosed. The memory includes a plurality of word lines, a first bit line, a second bit line, a third bit line, and a plurality of cells. The word lines are sequentially disposed in parallel. The first, the second, and the thi
7928709 Voltage regulator and AC-DC converter April 19, 2011
A voltage regulator is provided. An input node receives an input voltage. An output node provides a supply voltage. A first transistor is coupled between the input node and a node. A first resistor is coupled between the input node and a gate of the first transistor. A second transistor
7916519 Burn-in methods for static random access memories and chips March 29, 2011
A burn-in method for SRAMs and chips. For a memory cell of the SRAM, the SRAM burn-in method controls the control signals of the memory cell to generate current paths to pass through the memory cell, the corresponding bit-line and the corresponding bit-line-bar. The contacts/vias in the
7875930 Semiconductor structure having an enlarged finger shaped region for reducing electric field dens January 25, 2011
The invention provides a semiconductor structure. A first type body doped region is deposited on a first type substrate. A first type heavily-doped region having a finger portion with an enlarged end region is deposited on the first type body doped region. A second type well region is
7872462 Bandgap reference circuits January 18, 2011
A bandgap reference circuit is provided. An input node receives a supply voltage. An output node provides a reference voltage. A first transistor is coupled between the input node and the output node and has a first control terminal. A resistor is coupled between the input node and the
7863147 Semiconductor device and fabrication method thereof January 4, 2011
A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the
7838931 High voltage semiconductor devices with Schottky diodes November 23, 2010
High voltage semiconductor devices with Schottky diodes are presented. A high voltage semiconductor device includes an LDMOS device and a Schottky diode device. The LDMOS device includes a semiconductor substrate, a P-body region in a first region of the substrate, and an N-drift region
7821082 Method for increasing breaking down voltage of lateral diffused metal oxide semiconductor transi October 26, 2010
A lateral diffused metal oxide semiconductor transistor is disclosed. A p-type bulk is disposed on a substrate. An n-type well region is disposed in the p-type bulk. A plurality of field oxide layers are disposed on the p-type bulk and the n-type well region. A gate structure is disposed
7821070 Trig modulation electrostatic discharge (ESD) protection devices October 26, 2010
Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region a
7795083 Semiconductor structure and fabrication method thereof September 14, 2010
The invention provides a method for forming a semiconductor structure. A plurality of first type well regions is formed in the first type substrate. A plurality of second type well regions and a plurality of second type bar doped regions are formed in the first type substrate by a do
7759245 Semiconductor device fabricating method July 20, 2010
A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises providing a substrate with a logic device region and a memory device region. A logic device with a first silicide region and a first silicide block region and a memory device
7755925 Static random access memory July 13, 2010
A static random access memory comprising a column driver, a row driver, a cell, and a control unit is disclosed. The column driver selects a first word line or a second word line. The row provides data to a first bit line and a second bit line. The data of the first bit line is opposite
7755143 Semiconductor device July 13, 2010
A semiconductor device is described. The semiconductor device comprises a protected device in a protected device area of a substrate. An electrostatic discharge power clamp device comprising an outer first guard ring and an inner second guard ring is in a guard ring area of the subst
7745343 Method for fabricating semiconductor device with fuse element June 29, 2010
A method for fabricating a semiconductor device with a fuse element includes providing a semiconductor structure with a fuse element formed over a first device region thereof. A first interlayer dielectric layer, an etching stop layer and a second interlayer dielectric layer are sequ
7737674 Voltage regulator June 15, 2010
A voltage regulator. A pass element has a control gate and outputs an output voltage according to an input voltage and a control signal received from the control gate. A feedback circuit generates a feedback signal according to the output voltage. A bandgap circuit generates a refere
7706203 Memory system April 27, 2010
A memory system is provided, comprising at least one memory unit and a source power supply circuit. Each memory unit is coupled between a source voltage and a ground voltage and accesses digital data according to a word line signal and a bit line signal. The source power supply circuit
7682955 Method for forming deep well of power device March 23, 2010
The invention provides a method for forming a deep well region of a power device, including: providing a substrate with a first sacrificial layer thereon; forming a first patterned mask layer on the first sacrificial layer exposing a first open region; performing a first doping process t
7655978 Semiconductor structure February 2, 2010
A semiconductor structure including a substrate, a first well, a second well, a third well, a first doped region, and a second doped region. The substrate includes a first conductive type. The first well includes a second conductive type and is formed in the substrate. The second well
7599160 Electrostatic discharge protection circuits October 6, 2009
An electrostatic discharge (ESD) protection circuit is provided. A transistor is coupled between a node and a ground, and has a gate coupled to the ground. A diode chain is coupled between the node and a pad, and comprises a plurality of first diodes connected in series, wherein the
7579658 Devices without current crowding effect at the finger's ends August 25, 2009
ESD protection devices without current crowding effect at the finger's ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the NMOS or PMOS device structure is changed by the proposed new structures, therefore the MM ESD
7476934 Structure for an LDMOS transistor and fabrication method thereof January 13, 2009
A structure for an LDMOS transistor has a horseshoe-shaped gate layer formed on an N-type layer of a semiconductor silicon substrate, in which the gate layer comprises a transverse-extending area, a first lengthwise-extending area connected to a left end of the transverse-extending a
7369419 Voltage converter May 6, 2008
A voltage converter comprises an input terminal receiving a DC input voltage, an output terminal outputting an output voltage, a first switch coupled between a first node and the input terminal, a second switch coupled between the input terminal and a second node, a first capacitor c
7242070 Deep trench isolation structure of a high-voltage device and method for forming thereof July 10, 2007
A deep trench isolation structure of a high-voltage device and a method of forming thereof. An epitaxial layer with a second type conductivity is formed on a semiconductor silicon substrate with a first type conductivity. A deep trench passes through the epitaxial layer. An ion diffu
7217616 Non-volatile memory cell and method of forming the same May 15, 2007
A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the
7129546 Electrostatic discharge protection device October 31, 2006
An ESD protection device. The ESD protection device has a substrate; a channel region, a source region, and a drain region. The channel region is formed on a predetermined area of a surface of the substrate, the channel region has a first side and a second side. The source region is
7129134 Fabrication method for flash memory source line and flash memory October 31, 2006
A fabrication method for flash memory. The method comprises providing a substrate, and a first insulation layer, a first conductive layer, a second insulation layer thereon. The second insulation layer is patterned to form a first opening and reveal a part of the first conductive layer,
7115938 Non-volatile memory cell and method of forming the same October 3, 2006
A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the
7102421 Dynamically adjustable on-chip supply voltage generation September 5, 2006
A voltage regulation scheme for an on-chip voltage generator includes a voltage sensing circuit (VSC) and a configurable buffer circuit (CBC) to regulate the on-chip voltage generator. The CBC generates an output signal that is received by the on-chip voltage generator to activate and
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