| Patent Number |
Title Of Patent |
Date Issued |
| 7599160 |
Electrostatic discharge protection circuits |
October 6, 2009 |
| An electrostatic discharge (ESD) protection circuit is provided. A transistor is coupled between a node and a ground, and has a gate coupled to the ground. A diode chain is coupled between the node and a pad, and comprises a plurality of first diodes connected in series, wherein the |
| 7579658 |
Devices without current crowding effect at the finger's ends |
August 25, 2009 |
| ESD protection devices without current crowding effect at the finger's ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the NMOS or PMOS device structure is changed by the proposed new structures, therefore the MM ESD |
| 7476934 |
Structure for an LDMOS transistor and fabrication method thereof |
January 13, 2009 |
| A structure for an LDMOS transistor has a horseshoe-shaped gate layer formed on an N-type layer of a semiconductor silicon substrate, in which the gate layer comprises a transverse-extending area, a first lengthwise-extending area connected to a left end of the transverse-extending a |
| 7369419 |
Voltage converter |
May 6, 2008 |
| A voltage converter comprises an input terminal receiving a DC input voltage, an output terminal outputting an output voltage, a first switch coupled between a first node and the input terminal, a second switch coupled between the input terminal and a second node, a first capacitor c |
| 7242070 |
Deep trench isolation structure of a high-voltage device and method for forming thereof |
July 10, 2007 |
| A deep trench isolation structure of a high-voltage device and a method of forming thereof. An epitaxial layer with a second type conductivity is formed on a semiconductor silicon substrate with a first type conductivity. A deep trench passes through the epitaxial layer. An ion diffu |
| 7217616 |
Non-volatile memory cell and method of forming the same |
May 15, 2007 |
| A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the |
| 7129546 |
Electrostatic discharge protection device |
October 31, 2006 |
| An ESD protection device. The ESD protection device has a substrate; a channel region, a source region, and a drain region. The channel region is formed on a predetermined area of a surface of the substrate, the channel region has a first side and a second side. The source region is |
| 7129134 |
Fabrication method for flash memory source line and flash memory |
October 31, 2006 |
| A fabrication method for flash memory. The method comprises providing a substrate, and a first insulation layer, a first conductive layer, a second insulation layer thereon. The second insulation layer is patterned to form a first opening and reveal a part of the first conductive layer, |
| 7115938 |
Non-volatile memory cell and method of forming the same |
October 3, 2006 |
| A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the |
| 7102421 |
Dynamically adjustable on-chip supply voltage generation |
September 5, 2006 |
| A voltage regulation scheme for an on-chip voltage generator includes a voltage sensing circuit (VSC) and a configurable buffer circuit (CBC) to regulate the on-chip voltage generator. The CBC generates an output signal that is received by the on-chip voltage generator to activate and |
| 7098522 |
High voltage device with ESD protection |
August 29, 2006 |
| A high voltage device. A high voltage MOS transistor is applied in the ESD protection device to the structure of which a doped region is added, generating a parasitic semiconductor controlled rectifier (SCR) having a shorter discharge path such that the SCR has faster response enhancing |
| 7092600 |
Method for fabricating Fiber Bragg Grating elements and planar light circuits made thereof |
August 15, 2006 |
| A method for fabricating Fiber Bragg Grating elements and planar light circuits made thereof. A mask having a predetermined pattern and a wafer are provided, wherein a light-guiding channel filled with light-guiding substance is formed on the wafer. A photoresist layer is then formed to |
| 7041572 |
Fabrication method for a deep trench isolation structure of a high-voltage device |
May 9, 2006 |
| A fabrication method for a semiconductor device. On a semiconductor silicon substrate with a first type conductivity, an epitaxial layer with a second type conductivity and an oxide layer on the epitaxial layer are formed with at least a deep trench. Ion implantation is used to form an |
| 7034873 |
Pixel defect correction in a CMOS active pixel image sensor |
April 25, 2006 |
| Effectively defect free images are obtained from CMOS image sensors through a two step method in which the addresses of bad pixels are recorded during sensor testing and stored in an on-chip directory. Then, during sensor readout, each pixel address is checked to determine if it repr |
| 7028361 |
Cleaning assembly |
April 18, 2006 |
| A cleaning assembly for a pipe. The assembly comprises a sleeve, at least one magnet, and at least one moveable hollow member. The sleeve is moveably disposed on the outer wall of the pipe. The at least one magnet is disposed on the inner surface of the sleeve. The at least one moveable |
| 6995850 |
Monitoring apparatus for polishing pad and method thereof |
February 7, 2006 |
| A monitoring apparatus for a polishing pad. A chemical mechanical polishing machine, a polishing pad, a measuring device, and a display device are provided. The polishing pad is situated in a predetermined position in the chemical mechanical polishing machine. The measuring device is |
| 6978066 |
Method for fabricating fiber bragg grating elements and planar light circuits made thereof |
December 20, 2005 |
| A method for fabricating Fiber Bragg Grating elements and planar light circuits made thereof. A mask having a predetermined pattern and a wafer are provided, wherein a light-guiding channel filled with light-guiding substance is formed on the wafer. A photoresist layer is then formed to |
| 6972471 |
Deep trench isolation structure of a high-voltage device and method for forming thereof |
December 6, 2005 |
| A deep trench isolation structure of a high-voltage device and a method of forming thereof. An epitaxial layer with a second type conductivity is formed on a semiconductor silicon substrate with a first type conductivity. A deep trench passes through the epitaxial layer. An ion diffu |
| 6916702 |
Gate process and gate structure for an embedded memory device |
July 12, 2005 |
| A gate process and a gate process for an embedded memory device. A semiconductor silicon substrate has a memory cell area and a logic circuit area. A first dielectric layer is formed overlying the semiconductor silicon substrate, and then a gate structure is formed overlying the first |
| 6887756 |
Method of forming flash memory with protruded floating gate |
May 3, 2005 |
| A method of forming a flash memory with a protruded floating gate. A substrate is provided. An isolation area and a plurality of patterned conductive layers are sequentially formed on the substrate. The isolation area protrudes from the upper surface of the substrate to isolate the p |
| 6875658 |
High-voltage device with improved punch through voltage and process for same compatible with low |
April 5, 2005 |
| A high-voltage device with improved punch through voltage. A semiconductor silicon substrate has a high-voltage device region on which a gate structure is patterned. A lightly doped region is formed in the substrate and lateral to the gate structure. A spacer is formed on the sidewall of |
| 6835636 |
Method for fabricating source/drain devices |
December 28, 2004 |
| A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed on the semiconductor substrate, and a hard mask layer formed on the gate. A first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped ar |
| 6797933 |
On-chip design-for-testing structure for CMOS APS (active pixel sensor) image sensor |
September 28, 2004 |
| Apparatus and methods for testing an active pixel sensor ensure that a signal proportional to the quantity of light energy impinging on the active pixel sensor is reliably and accurately captured and made available for further on processing the rest of the APS system circuitry. The a |
| 6797574 |
Method of fabricating W/TiN gate for MOSFETS |
September 28, 2004 |
| A dielectric layer is etched to form an opening in dielectric layer. A gate oxide layer is formed on semiconductor substrate in said opening. A barrier conductor is formed along the surface of the opening. A metal layer is formed on the barrier conductor and refilled into the opening. A |
| 6764867 |
Reticle option layer detection method |
July 20, 2004 |
| A new method of detecting a reticle option layer in an integrated circuit device has been achieved. The method may be applied to detect the presence of the threshold voltage implantation reticle option layer by direct die probing or by probing a pin of a package integrated circuit. The c |
| 6762096 |
Method for forming a polysilicon spacer with a vertical profile |
July 13, 2004 |
| A method of forming a polysilicon spacer with a vertical profile. A dielectric layer and a sacrificial layer are successively deposited to cover the entire surface of a polysilicon layer that covers an insulating structure. Then, CMP is used to remove parts of the sacrificial layer, the |
| 6730958 |
Nonvolatile memory device with reduced floating gate and increased coupling ratio and manufactur |
May 4, 2004 |
| A nonvolatile memory device with a reduced size floating gate and an increased coupling ratio is disclosed. The nonvolatile memory device includes two isolation structures protruding above a semiconductor substrate. Two dielectric spacers are disposed on a pair of opposing sidewalls |
| 6730191 |
Coaxial dressing for chemical mechanical polishing |
May 4, 2004 |
| A polishing apparatus of a semiconductor wafer by a chemical-mechanical polishing method including a polishing platen having an upper surface on which a polishing pad is attached. The polishing platen is rotated in one direction along a central axis. A plurality of coaxial polishing-dres |
| 6713338 |
Method for fabricating source/drain devices |
March 30, 2004 |
| A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed thereon, a first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor su |
| 6680231 |
High-voltage device process compatible with low-voltage device process |
January 20, 2004 |
| A high-voltage device process compatible with a low-voltage device process. A high-voltage device area and a low-voltage device area are defined on an epitaxial layer of a semiconductor substrate. After forming a plurality of first gate structures on the high-voltage device area, a P-bod |
| 6665160 |
Voltage control component for ESD protection and its relevant circuitry |
December 16, 2003 |
| The present invention proposes an ESD protection circuit and its related circuits, suitable in an integrated circuit (IC), and coupled between a first pad and a second pad. When a power supply is provided to the IC, a bias generator generates a bias voltage to close the protection compon |
| 6650105 |
EPROM used as a voltage monitor for semiconductor burn-in |
November 18, 2003 |
| An EPROM is configured in a special way to monitor in situ the applied voltage to semiconductor product in a burn-in test and capture the maximum value of the applied voltage during the test. This technique operates off the threshold shift mechanism in which gate bias induces electrons a |
| 6645869 |
Etching back process to improve topographic planarization of a polysilicon layer |
November 11, 2003 |
| An etching back process to improve topographic planarization of a polysilicon layer. First, a polysilicon layer is formed to fill a contact hole between two adjacent insulating structures and cover the entire surface of a semiconductor substrate to a predetermined height, in which a |
| 6621673 |
Two-stage ESD protection circuit with a secondary ESD protection circuit having a quicker trigge |
September 16, 2003 |
| A two-stage ESD protection circuit coupled between an I/O pad and a power rail is provided in the present invention. The two-stage ESD protection circuit has a primary ESD protection circuit and a secondary ESD circuit. The trigger-on rate of the secondary ESD protection circuit is sped |
| 6596589 |
Method of manufacturing a high coupling ratio stacked gate flash memory with an HSG-SI layer |
July 22, 2003 |
| A stacked-gate flash memory cell includes a trench formed in a substrate and a tunneling oxide layer formed on the substrate. A first part of the floating gate is formed on the tunneling oxide layer. A protruding isolation filler is formed in the trench and protrudes over the upper s |
| 6590264 |
Hybrid diodes with excellent ESD protection capacity |
July 8, 2003 |
| Hybrid diodes with excellent ESD protection capacity. Each hybrid diode has two diodes: one is a poly-bounded diode formed as a junction between a substrate and a diffusion region thereon, the other is a poly diode formed as a poly gate having two regions with different conductivity. The |
| 6589840 |
Nonvolatile memory device with reduced floating gate and increased coupling ratio and manufactur |
July 8, 2003 |
| A nonvolatile memory device with a reduced size floating gate and an increased coupling ratio is disclosed. The nonvolatile memory device includes two isolation structures protruding above a semiconductor substrate. Two dielectric spacers are disposed on a pair of opposing sidewalls |
| 6576384 |
Mask image scanning exposure method |
June 10, 2003 |
| A dynamic mask exposure method and system includes a support for a workpiece, a source of a beam of exposure radiation, and a transmissive dynamic mask with orthogonally arranged matrices of actuator lines and binary pixel units which are opaque or transparent as a function of contro |
| 6565759 |
Etching process |
May 20, 2003 |
| A method for etching a pattern within a silicon containing dielectric layer upon a substrate employed within a microelectronics fabrication, employing a plasma activated reactive gas mixture, with layer material etch rate, etch rate ratio and pattern aspect ratio controlled by controllin |
| 6559508 |
ESD protection device for open drain I/O pad in integrated circuits with merged layout structure |
May 6, 2003 |
| An open drain driver circuit and a Vss to Vdd FET with a merged layout structure are formed to provide a short path for an ESD current from an associated pad and either Vss or Vdd. The short path reduces the IR drop in the path and thereby maintains a lower voltage at the pad during an E |
| 6555434 |
Nonvolatile memory device and manufacturing method thereof |
April 29, 2003 |
| A nonvolatile memory device with a high coupling ratio is disclosed. The nonvolatile memory device includes a semiconductor substrate having shallow trench isolation (STI) formed therein and active regions defined. On the active regions, a floating gate is provided with a gate dielectric |
| 6555433 |
Method of manufacture of a crown or stack capacitor with a monolithic fin structure made with a |
April 29, 2003 |
| In this process, a capacitor core is formed on a semiconductor device with a first conductive sublayer in contact with a plug. First form a stack of alternately doped and undoped oxide layers on the sublayer with the stack comprising a bottom layer formed on top of the sublayer and each |
| 6548353 |
Method of making nonvolatile memory device having reduced capacitance between floating gate and |
April 15, 2003 |
| This invention discloses a method of making a nonvolatile memory device, wherein the capacitance between the floating gate and the substrate is reduced to result in a high capacitive coupling ratio. First, a substrate with shallow trench isolation (STI) structures protruding above the |
| 6537880 |
Method of fabricating a high density NAND stacked gate flash memory device having narrow pitch i |
March 25, 2003 |
| A process for fabricating a flash memory cell with increased floating gate to control gate overlap, has been developed. The process features forming the active device region of the flash memory cell in a narrow space of a semiconductor substrate, located between STI regions. The increase |
| 6534818 |
Stacked-gate flash memory device |
March 18, 2003 |
| A novel flash memory structure is disclosed, which includes a tunnel oxide layer on a semiconductor substrate, an array of gate electrode stacks formed on the tunnel oxide layer, and alternating source/drain regions formed between the stacks. A first dielectric layer is formed over the |
| 6529427 |
Test structures for measuring DRAM cell node junction leakage current |
March 4, 2003 |
| A method and methodology is provided for measuring ultra-low leakage current in DRAM devices. The invention provides a method and structures that are not limited to a trade-off between the number of contact points that are established to do the measurement and test accuracy, that can |
| 6528402 |
Dual salicidation process |
March 4, 2003 |
| A dual salicidation process has the steps of: covering a sacrificial layer on the top of a polysilicon gate conductor; performing a thermal oxidization process to form a poly-oxide spacer on the sidewall of the polysilicon gate conductor; forming source/drain regions within the subst |
| 6524939 |
Dual salicidation process |
February 25, 2003 |
| A dual salicidation process is used on a semiconductor substrate which has a gate dielectric, a polysilicon gate conductor patterned upon a predetermined area of the gate dielectric, a sacrificial layer patterned upon the polysilicon gate conductor, and LDD areas formed within the su |
| 6503764 |
Method of making in high density DRAM circuit having a stacked capacitor |
January 7, 2003 |
| The present invention discloses a method of making stacked Metal-Insulator-Metal capacitor in high density DRAM circuit, comprising the steps of: forming a contact plug in an insulating layer on a semiconductor substrate; forming a first conductor layer, a first barrier metal layer, |
| 6498064 |
Flash memory with conformal floating gate and the method of making the same |
December 24, 2002 |
| A flash memory comprises a substrate having trenches formed therein. A tunneling oxide is formed on a surface of the substrate and adjacent to the trenches. A raised isolation fillers is formed in the trenches and protruding over an upper surface of the substrate, thereby forming a c |
