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VLSI Technology, Inc. Patents
VLSI Technology, Inc.
San Jose, CA
No. of patents:

Patent Number Title Of Patent Date Issued
RE36893 Anti-fuse structure for reducing contamination of the anti-fuse material October 3, 2000
An anti-fuse structure formed in accordance with the present invention includes a conductive layer base. A layer of anti-fuse material overlies the conductive base layer. On top of the anti-fuse layer is an insulating layer, in which a via hole is formed to the anti-fuse layer. The later
RE35671 Predictive capacitance layout method for integrated circuits November 25, 1997
A method for designing a circuit layout which includes the steps of supplying a predictive capacitance value for at least one net of a circuit layout, and placing and routing all nets of the circuit layout using at least one predictive capacitance value as a layout design constraint.
6549563 Methods and apparatus for use in generating spreading sequences for multiple modes of communicat April 15, 2003
In one example described, a data sequence generator for use in spread spectrum communications includes one or more read-only memories (ROMs) which have first and second spreading sequences stored therein. The first spreading sequence is associated with a first mode of communication,
6539049 Device and method for maintaining time synchronous with a network master time March 25, 2003
An integrated circuit device includes a clock generator having a primary input for coupling to a primary reference frequency source, a secondary input for coupling to a secondary reference frequency source, and an output that produces a primary digital transceiver clock signal having a
6487242 Method and apparatus for VCO modulation in a communication system November 26, 2002
A VCO modulator controller including a ROM memory storing a number of waveform maps, a counter coupled to the ROM memory and capable of developing a sequence of ROM addresses, a temporal bit generator responsive to a data stream to develop a next bit Nb, a current bit Cb, and a past
6472253 Programmable semiconductor device structures and methods for making the same October 29, 2002
A programmable device and methods for making the programmable device are provided. The programmable device includes a link metallization line with an oxide layer defined above the link metallization line. A via hole is patterned in the oxide layer which defines a path to the link met
6452959 Method of and apparatus for generating data sequences for use in communications September 17, 2002
A method of generating one or more pseudorandom noise (PN) sequences for use in spread spectrum communications includes the steps of providing data at an input of memory which stores bits associated with a pseudorandom noise (PN) sequence: changing the data; and for each of a plurality o
6424180 Digital phase shift amplification and detection system and method July 23, 2002
A digital phase shift amplification and detection system and method. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region which amplifies any timing changes in the signal. The amplified signal is fed into a detection circuit c
6411367 Modified optics for imaging of lens limited subresolution features June 25, 2002
A system and method is disclosed for enhancing an optical lithography process by capturing light diffracted from a mask having features to be exposed onto a wafer. In one embodiment, a system of the present invention has in place a mask, a wafer and a reduction lens such that the reducti
6410440 Method and apparatus for a gaseous environment providing improved control of CMP process June 25, 2002
A method of using a gaseous environment providing improved control of CMP process. In one embodiment, the method comprises several steps. One step involves placing a semiconductor wafer onto a polishing pad of a CMP machine. A subsequent step dispenses a slurry onto the polishing pad.
6400728 Method and system for detecting user data types in digital communications channels and optimizin June 4, 2002
A dynamic error correction system for a digital data transmission system. A transmitter adapted to encode user data into a signal is included within the system. A receiver receives the signal and decodes the user data encoded thereon. The signal is transmitted from the transmitter to the
6397279 Smart retry system that reduces wasted bus transactions associated with master retries May 28, 2002
The present invention comprises a smart retry system for agents in a computer system. The smart retry system of the present invention includes a master agent, a slave agent, an arbiter, and smart retry logic components, all adapted to be coupled to a bus. The bus permits agents coupl
6380092 Gas phase planarization process for semiconductor wafers April 30, 2002
A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric
6380001 Flexible pin count package for semiconductor device April 30, 2002
A package for a semiconductor device and a method for packaging a semiconductor device are disclosed. The semiconductor package uses a tape which allows for the production of packaged semiconductor devices having different contact patterns. The contact pattern is configured to the re
6378044 Method and system for cache replacement among configurable cache sets April 23, 2002
A method and system for cache replacement among configurable cache sets. In one embodiment, the present invention identifies a cache location corresponding to uncached data received from main memory and determines a data type for the uncached data. The present invention then examines the
6377581 Optimized CPU-memory high bandwidth multibus structure simultaneously supporting design reusable April 23, 2002
An optimized CPU-memory high bandwidth multibus structure simultaneously supporting design reusable blocks. A system in accordance with the present invention communicatively couples the internal components (e.g., CPU, memory, etc.) and peripheral devices (e.g., display, keyboard, etc.) o
6374398 Efficient database for die-per-wafer computations April 16, 2002
A method and system thereof for efficiently computing the number of dies per wafer and the corresponding number of stepper shot counts. Dimensions for a die and the size of the wafer are received. The dimensions comprise a die element size that is a function of a scribe lane width, a gua
6372522 Use of optimized film stacks for increasing absorption for laser repair of fuse links April 16, 2002
A system for repairable interconnect links using laser energy in a semiconductor integrated circuit die. The integrated circuit die is fabricated to include a plurality of interconnect links. At least a first and a second interconnect element are included in the integrated circuit di
6369427 Integrated circuitry, interface circuit of an integrated circuit device, and cascode circuitry April 9, 2002
The present invention includes integrated circuitry, an interface circuit of an integrated circuit device, cascode circuitry, method of protecting an integrated circuit, method of operating integrated circuitry, and method of operating cascode circuitry. One aspect of the present inventi
6363466 Interface and process for handling out-of-order data transactions and synchronizing events in a March 26, 2002
An interface and process for re-ordering data transactions between a master device and a target device. The present invention applies to target devices that interface to master devices such that both masters and slaves are capable of handling the re-ordering of outstanding requests. In s
6360754 Method of protecting quartz hardware from etching during plasma-enhanced cleaning of a semicondu March 26, 2002
The present invention is a method of suppressing etchrate of quartz hardware in semiconductor processing chamber during plasma-enhanced cleaning. In one embodiment, the method of the present invention includes the steps of: (a) introducing a mixture of fluorocarbon gas, oxygen, and w
6356610 System to avoid unstable data transfer between digital systems March 12, 2002
A system to avoid unstable data transfer between digital systems. The present invention includes a system that enables digital systems to communicate while avoiding unstable data transfer, which can result in a loss of data or signal distortion. For instance, the present invention in
6355576 Method for cleaning integrated circuit bonding pads March 12, 2002
A method for cleaning bonding pads on a semiconductor device, as disclosed herein, includes treating the bonding pads with a CF.sub.4 and water vapor combination. In the process, the water vapor breaks up and the hydrogen from the water vapor couples to fluorine residue on the bonding pa
6354921 System for cross stream regassifier for improved chemical mechanical polishing in the manufactur March 12, 2002
An apparatus to induce very small bubbles of gas into a stream of deionized water without allowing large bubbles to be entrained is disclosed for use in Chemical Mechanical Polishing for semiconductor manufacture. The apparatus includes a cylinder possessing a central axis positioned
6353904 Method of automatically generating new test programs for mixed-signal integrated circuit based o March 5, 2002
A method of automatically generating a mixed-signal test program. The method according to one embodiment of the present invention is implemented in software in the form of two software processes. The first software process of the present embodiment includes a test-block extraction proces
6353368 VCO circuit using negative feedback to reduce phase noise March 5, 2002
A low phase noise CMOS voltage controlled oscillator (VCO) circuit. The VCO circuit includes a bias circuit and a VCO cell coupled to the bias circuit. The VCO cell includes a VCO output for transmitting a VCO output signal. A frequency to voltage converter is coupled to receive the VCO
6353261 Method and apparatus for reducing interconnect resistance using an interconnect well March 5, 2002
An apparatus for reducing interconnect resistance using optimized trench geometry. One embodiment comprises an interconnect line and an interconnect well. The interconnect line, comprised of a conductive material, has a depth and exists in a first circuit layer of a multilayered Inte
6346032 Fluid dispensing fixed abrasive polishing pad February 12, 2002
The present invention is a fluid dispensing fixed abrasive polishing pad CMP system and method that utilizes fixed abrasive components to remove a portion or entire layer of a wafer while dispensing a fluid without suspended abrasive particles onto the wafer surface. A fluid dispensing
6341998 Integrated circuit (IC) plating deposition system and method January 29, 2002
The present invention system and method facilitates efficient material deposition and wafer planarization during IC wafer fabrication. The present invention is particularly useful in facilitating efficient copper deposition and manufacturing of interconnections between components of an
6341362 Extended symbol Galois field error correcting device January 22, 2002
An extended symbol Galois field error correcting device is provided. The device includes a singly-extended Reed-Solomon encoder configured to generate an encoded codeword, c(x). The device also includes a channel medium that is signal coupled with the singly-extended Reed-Solomon enc
6338158 Custom IC hardware modeling using standard ICs for use in IC design validation January 8, 2002
Testing and validation of custom IC designs is performed using standard ICs. Highly complex integrated circuits, instead of being designed at the gates and flops level, are typically designed using standardized cell libraries that allow for widespread, systematic design reuse. Such l
6330623 System and method for maximizing DMA transfers of arbitrarily aligned data December 11, 2001
A direct memory access engine (DMA) system and method for maximizing DMA transfers of arbitrarily aligned data. The present invention utilizes physical region descriptors (PRD) stored in memory to track locations and descriptions of scattered data in a main memory. The direct memory acce
6327513 Methods and apparatus for calculating alignment of layers during semiconductor processing December 4, 2001
Methods and apparatus for calculating alignment of layers during semiconductor processing are described. In one embodiment, first and second alignment targets are formed over a substrate and include respective pairs of first and second alignment target edges. The second alignment tar
6326283 Trench-diffusion corner rounding in a shallow-trench (STI) process December 4, 2001
An isolation structure on an integrated circuit is formed using a shallow trench isolation process. A layer of buffer oxide is formed on a substrate. A layer of nitride is formed on the layer of buffer oxide. The layer of nitride and the layer of buffer oxide are patterned to form a
6324663 System and method to test internal PCI agents November 27, 2001
The present invention is an on board internal peripheral component interconnect (PCI) bus tester for testing internal components of a microelectronic chip. The present invention includes internal PCI testing agents that facilitate the application of test vectors to internal PCI agent
6323520 Method for forming channel-region doping profile for semiconductor device November 27, 2001
A method for forming a semiconductor device with a doped channel-region, and the device formed therefrom. In one embodiment, the method invention is comprised of two principal steps. The first step is to provide a semiconductor substrate to which the following process steps can be pe
6321321 Set-associative cache-management method with parallel and single-set sequential reads November 20, 2001
A set-associative cache-management method utilizes both parallel reads and single-cycle single-set reads. The parallel reads involve accessing data from all cache sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the access
6319796 Manufacture of an integrated circuit isolation structure November 20, 2001
Disclosed are techniques to provide an integrated circuit, including the provision of improved integrated circuit isolation structures. The techniques include forming a number of trenches in an integrated circuit substrate to define a number of substrate regions that are to be electr
6317763 Circuits, barrel shifters, and methods of manipulating a bit pattern November 13, 2001
The present invention provides for a circuit comprising: an input operable to receive a bit pattern; a shifter configured to selectively shift the bit pattern; a data output operable to output the bit pattern; and a sign extension operator coupled with the data output and operable to pro
6316834 Tungsten plugs for integrated circuits and method for making same November 13, 2001
A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer
6315645 Patterned polishing pad for use in chemical mechanical polishing of semiconductor wafers November 13, 2001
A patterned polishing pad adapted for use in a wafer polishing machine. The patterned polishing pad has a polishing surface adapted to contact frictionally a semiconductor wafer being polished in a chemical mechanical polishing machine. The polishing surface has a first region and a seco
6314154 Non-power-of-two Gray-code counter and binary incrementer therefor November 6, 2001
Non-power-of-two Gray-code counters, including modulos 10, 12, 14, and 22 are disclosed, along with a sequencing method they employ. Each counter includes a register for storing an N-bit, e.g., 4-bit, Gray-code count. The count is converted to binary code by a Gray-to-binary-code counter
6313542 Method and apparatus for detecting edges under an opaque layer November 6, 2001
The present invention is directed to a method and apparatus for detecting edges through one or more opaque, planarized layers of material. Exemplary embodiments can take full advantage of decreased size geometries associated, such as 0.25 micron technologies, without suffering inaccu
6311318 Design for test area optimization algorithm October 30, 2001
A computer implemented circuit synthesis system includes a memory, an automatic test pattern generation (ATPG) algorithm, and processing circuitry. The memory is configured to provide a database, and is operative to store a netlist including nets of an integrated circuit under design
6311248 Method and system for optimized data transfers in a mixed 64-bit/32-bit PCI environment October 30, 2001
A method for optimizing the performance of a 64-bit PCI initiator when transferring a 64-bit data via a 64-bit PCI bus. The 64-bit PCI initiator receives a single 64-bit data for transfer via the 64-bit PCI bus. The 64-bit PCI initiator breaks the 64-bit data into a first 32-bit data and
6309948 Method for fabrication of a semiconductor device October 30, 2001
A method for forming a semiconductor structure on an active area mesa with minimal loss of field oxide deposited in isolation trenches adjacent the mesa. The trench insulating material is protected by an etch barrier layer having at least a partial resistance to etchants used in further
6309937 Method of making shallow junction semiconductor devices October 30, 2001
Disclosed is a technique to provide an integrated circuit substrate with a transistor gate member that has opposing sidewalls. A first spacer extends from one of the sidewalls and a second spacer extends from another of the sidewalls. A source region and a drain region of the substrate a
6304560 Personal handy-phone system wireless local loops and methods of transmitting information within October 16, 2001
The present invention provides methods of transmitting information within a personal handy-phone system wireless local loop and personal handy-phone system wireless local loops. One embodiment of a personal handy-phone system wireless local loop according to the present invention compris
6303504 Method of improving process robustness of nickel salicide in semiconductors October 16, 2001
After a metal deposition preclean, a very thin titanium layer is deposited followed by a thick nickel layer on a semiconductor silicon substrate. The titanium and nickel are deposited sequentially in a vacuum cluster tool to prevent oxidation of titanium in air. The silicon substrate and
6301632 Direct memory access system and method to bridge PCI bus protocols and hitachi SH4 protocols October 9, 2001
The present invention is a direct access bridge for translating messages between a first protocol and a second protocol via a first component interface and a second component interface. The first and second component interfaces are adapted to respectively couple to a first and second

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