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United Microelectronics Corporation Patents
Assignee:
United Microelectronics Corporation
Address:
Hsinchu, TW
No. of patents:
533
Patents:


1 2 3 4 5 6 7 8 9 10 11










Patent Number Title Of Patent Date Issued
RE39274 Voltage down converter with switched hysteresis September 12, 2006
A voltage down converter with hysteresis generator combining a hysteresis signal to a reference voltage and an output voltage feedback signal applied to a comparator. The hysteresis generator is coupled to a control signal giving advance notice of when a high current load is to be ac
8588020 Sense amplifier and method for determining values of voltages on bit-line pair November 19, 2013
A sense amplifier and a method for determining the values of the voltages on a bit-line pair are provided. The sense amplifier comprises a first delay chain and a second delay chain. The first delay chain is electrically connected to a bit line and configured for receiving a clock si
8587128 Damascene structure November 19, 2013
A damascene structure includes a conductive layer, a first dielectric layer, a first barrier metal layer, a barrier layer, and a second barrier metal layer sequentially formed on the conductive layer. The first dielectric layer having a via therein. The barrier layer is comprised of
8575034 Fabricating method of semiconductor element November 5, 2013
The present invention relates to a fabricating method of a semiconductor element. First, a substrate is provided and a first layout structure having a first width is formed on the substrate. Then, an etching mask is formed to cover the first layout structure, and the etching mask exposes
8268712 Method of forming metal gate structure and method of forming metal gate transistor September 18, 2012
A method of forming metal gate transistor includes providing a substrate; forming a gate dielectric layer, a work function metal layer and a polysilicon layer stacked on the substrate; forming a hard mask and a patterned photoresist on the polysilicon layer; removing the patterned ph
8247838 Light emitting diode with semiconductor layer having different resistance at different regions August 21, 2012
A light emitting diode and a fabricating method thereof are provided. The method including the steps of sequentially forming a first-type semiconductor layer, a light emitting layer and a second-type semiconductor layer with a first region and a second region on a substrate. Next, an
8227890 Method of forming an electrical fuse and a metal gate transistor and the related electrical fuse July 24, 2012
The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack i
8093153 Method of etching oxide layer and nitride layer January 10, 2012
An exemplary method of patterning oxide layer and removing residual nitride includes steps of forming a first oxide layer, a nitride layer, a second oxide layer and a complex hard mask on a substrate in turn. The first oxide layer covers an insulating structure. The second oxide layer,
8071440 Method of fabricating a dynamic random access memory December 6, 2011
A method of fabricating a dynamic random access memory is provided. First, a substrate at least having a memory device area and a peripheral device area is provided, wherein an isolation structure and a capacitor are formed in the substrate of the memory device area, and an isolation
7890058 Game machine and information communication system using data carrier February 15, 2011
A game apparatus includes an apparatus body; and a plurality of small playing members each having a data carrier for transmitting driving electric power and performing mutual communications with the apparatus body. The number of points is added by the apparatus body when a change is
7718079 High density plasma chemical vapor deposition process May 18, 2010
A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. Fi
7552408 Method for performing design rule check on mask pattern data for an integrated circuit June 23, 2009
An improved system and method is disclosed for performing a design rule check on a proposed integrated circuit (IC) layout, and for creating customized design rule check command files. The individual layers of the IC (a system on chip--SOC) are separated into different regions having
7514014 High density plasma chemical vapor deposition process April 7, 2009
A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. Fi
7449407 Air gap for dual damascene applications November 11, 2008
An air gap structure and formation method for substantially reducing capacitance in a dual damascene based interconnect structure is disclosed. The air gap extends above, and may also additionally extend below, the damascene interconnects desired to be isolated thus minimizing fringi
7253095 Air gap formation method for reducing undesired capacitive coupling between interconnects in an August 7, 2007
An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects
7244653 Method and structure in the manufacture of mask read only memory July 17, 2007
A method and structure of manufacture of mask ROM device is provided. Firstly, a semiconductor structure is provided that comprises a first dielectric layer, a plurality of buried bit lines and a plurality of code areas, wherein each of the code areas is placed between two buried bit
7179740 Integrated circuit with improved interconnect structure and process for making same February 20, 2007
A semiconductor die and an associated low resistance interconnect located primarily on the bottom surface of such die is disclosed. This arrangement provides a flexible packaging structure permitting easy interconnected with other integrated circuits; in this manner, a number of such
7138329 Air gap for tungsten/aluminum plug applications November 21, 2006
An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects
7087464 Method and structure for a wafer level packaging August 8, 2006
A method and structure for a wafer level package is provided, which utilizes a plurality of spacer walls on a semiconductor wafer or a transparent substrate, which has the ability to decide the position of the sealant. As a result, the dimension of a device is decided by the position
7037802 Chemical mechanical polishing in forming semiconductor device May 2, 2006
A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the fol
7030466 Intermediate structure for making integrated circuit device and wafer April 18, 2006
A semiconductor die and an associated low resistance interconnect located primarily on the bottom surface of such die is disclosed. This arrangement provides a flexible packaging structure permitting easy interconnected with other integrated circuits; in this manner, a number of such
7018906 Chemical mechanical polishing for forming a shallow trench isolation structure March 28, 2006
A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relatively small active regions, is provided. The method comprises the f
6878627 Semiconductor device with cobalt silicide contacts and method of making the same April 12, 2005
A semiconductor device that includes cobalt-silicide based contacts is disclosed, as well as a process for making the same. Combinations of alloyed layers of Co--Ti-- along with layers of Co-- are arranged and heat treated so as to effectuate a silicide reaction on a silicon substrate.
6838357 Chemical mechanical polishing for forming a shallow trench isolation structure January 4, 2005
A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the follo
6838333 Semiconductor memory device and method of producing the same January 4, 2005
A semiconductor memory device has access transistors with a gate and a pair of impurity diffusion layers formed on a semiconductor substrate and memory capacitors with a storage node electrode and a cell plate electrode. The electrodes are connected to each other via a capacitive ins
6838310 Integrated circuit with improved interconnect structure and process for making same January 4, 2005
A semiconductor die and an associated low resistance interconnect located primarily on the bottom surface of such die is disclosed. This arrangement provides a flexible packaging structure permitting easy interconnected with other integrated circuits; in this manner, a number of such cir
6833293 Semiconductor device and method for manufacturing the same December 21, 2004
In a semiconductor device in which a source/drain and a wiring layer are connected to each other through an associated buried conductive layer, a separation width of the buried conductive layer on a upper portion of a gate electrode is made small in order to manufacture a highly reliable
6800911 Method of making a polycide interconnection layer having a silicide film formed on a polycrystal October 5, 2004
A semiconductor device has a semiconductor substrate and a conductive layer formed above the semiconductor substrate. The conductive layer has a silicon film, a silicide film formed on the silicon film, and a high melting-point metal film formed on the silicide film. The silicon film has
6790742 Chemical mechanical polishing in forming semiconductor device September 14, 2004
A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the fol
6785853 Integration type input circuit and method of testing it August 31, 2004
An input interface circuit is provided. The circuit includes an input transistor for receiving a digital input signal, a circuit for generating a reference value, and an integrating capacitor connected in series to a pair of current conducting electrodes of the input transistor for i
6767825 Etching process for forming damascene structure of the semiconductor July 27, 2004
First of all, a breakthrough process is performed for removing the polymer and oxidized residues remained on top surface of the hard-mask layers, wherein the breakthrough process utilizes a CF.sub.x -based mixed-gas, such as Ar/O.sub.2 /CF.sub.4, to slightly flush out the top surface of
6709879 Method for inspecting a pattern defect process March 23, 2004
A method for inspecting a pattern defect process is disclosed, in which a layer is formed to raise a signal-to-noise ratio on the substrate. This invention also provides a method for inspecting a pattern defect process. First of all, a substrate is provided. Then, a device profile is for
6680248 Method of forming dual damascene structure January 20, 2004
A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first
6657277 Method for forming antifuse via structure December 2, 2003
The present invention provides a method for forming an antifuse via structure. The antifuse via structures comprising a substrate that having a first conductive wire therein. Then, a first dielectric layer is formed on the substrate, and a photoresist layer is formed on the first die
6657229 Semiconductor device having multiple transistors sharing a common gate December 2, 2003
A semiconductor device has field shield isolation or trench type isolation between elements which suppresses penetration of field oxide into an element active region of the device. A common gate is located between two MOS transistors, which may be of opposite conductivity type. After gat
6596567 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING A IMPURITY LAYER DISPOSED BETWEEN A NON-DOP July 22, 2003
A semiconductor device has a semiconductor substrate and a conductive layer formed above the semiconductor substrate. The conductive layer has a silicon film, a silicide film formed on the silicon film, and a high melting-point metal film formed on the silicide film. The silicon film has
6593223 Method of forming dual damascene structure July 15, 2003
A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first
6521531 Method for selectively growing a conductive film to fill a contact hole February 18, 2003
Semiconductor device and method for manufacturing the same prevent the spread of a tungsten film out of an opening portion of a contact hole when the tungsten is grown in the contact hole and avoid inferior wiring shape and inter-wiring shirt-circuit. After a titanium/titanium nitride fi
6504217 Semiconductor device and a method of manufacturing the same January 7, 2003
A low-concentration impurity region and a high-concentration impurity region are formed respectively near the lower surface and the upper surface of an undoped polysilicon film by a first and second ion-implanations. A refractory metal film of tungsten or the like is formed on the po
6501148 Trench isolation for semiconductor device with lateral projections above substrate December 31, 2002
A semiconductor device includes a semiconductor substrate in which a trench for element isolation is formed, and an element isolation oxide film buried into the trench in such a manner that the element isolation oxide film is projected from the surface of the semiconductor substrate. The
6486040 Chemical mechanical polishing for forming a shallow trench isolation structure November 26, 2002
A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the follo
6470466 Integration type input circuit and method of testing it October 22, 2002
An input interface circuit is provided. The circuit includes an input transistor for receiving a digital input signal, a circuit for generating a reference value, and an integrating capacitor connected in series to a pair of current conducting electrodes of the input transistor for i
6448159 Chemical mechanical polishing for forming a shallow trench isolation structure September 10, 2002
A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the follo
6429509 Integrated circuit with improved interconnect structure and process for making same August 6, 2002
A semiconductor die and an associated low resistance interconnect located primarily on the bottom surface of such die is disclosed. This arrangement provides a flexible packaging structure permitting easy interconnect with other integrated circuits; in this manner, a number of such circu
6306744 Filter capacitor construction October 23, 2001
An integrated circuit having a voltage source and a plurality of conductive power bus tiers extending across the integrated circuit. Each of the power bus tiers are electrically coupled in parallel to the voltage source. The integrated circuit includes a filter capacitor having a first p
6285242 Reference voltage shifter September 4, 2001
A reference voltage generator for producing a reference voltage that is a preselected amount below a power supply voltage. A reference voltage source produces a first reference voltage that is VREF above the ground potential. A first load device coupled to the ground node and generates a
6285216 High speed output enable path and method for an integrated circuit device September 4, 2001
A high speed output enable path and method for an integrated circuit device which effectively minimizes the gate delays in the critical integrated circuit device data and clock paths and in which most amplification is added in the reset path which is not critical to access time. Based on
6277721 Salicide formation process August 21, 2001
A method of making a semiconductor device including a MOS transistor provides an insulator formed on a semiconductor substrate and a gate electrode formed on the insulator. Source/drain regions are formed within the substrate on either side of the gate electrode. A layer of titanium is
6272029 Dynamic regulation scheme for high speed charge pumps August 7, 2001
The present invention involves a charge pump including an input node coupled to receive an input voltage from a power voltage source and an oscillator unit generates a periodic enable regulator signal and a periodic reset signal. A regulator clock unit is coupled to the oscillator un
6235642 Method for reducing plasma charging damages May 22, 2001
A method for reducing plasma charging damages is disclosed. The method includes the following steps: define cell regions and scribe line regions on a substrate. Then, form a trench region on one of the scribe line regions wherein the bottom part of the trench region is in contact with
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