| Patent Number |
Title Of Patent |
Date Issued |
| RE40113 |
Method for fabricating gate oxide |
February 26, 2008 |
| A method for fabricating gate oxide includes a dilute wet oxidation process with additional nitrogen and moisture and an annealing process with a nitrogen base gas, wherein the volume of additional nitrogen is about .[.6-12.]. .Iadd.6-20 .Iaddend.times of the volume of the additional |
| D466500 |
Web pad |
December 3, 2002 |
|
| 7618856 |
Method for fabricating strained-silicon CMOS transistors |
November 17, 2009 |
| A semiconductor substrate having a first active region and a second active region for fabricating a first transistor and a second transistor is provided. A first gate structure and a second gate structure are formed on the first active region and the second active region and a first |
| 7617475 |
Method of manufacturing photomask and method of repairing optical proximity correction |
November 10, 2009 |
| A method of manufacturing a photomask is described. The graphic data of the photomask are provided, and than an optical proximity correction is performed to the graphic data. A process rule check is then performed to the graphic data with the optical proximity correction. When at least o |
| 7616297 |
Detachable detection window and detecting system |
November 10, 2009 |
| A detachable detection window suitable for being disposed on a sidewall of a plasma chamber is disclosed. The detachable detection window includes a base and a cannular tube. The base herein has a first linking-up part and a second linking-up part is formed at an end of the cannular tube |
| 7615434 |
CMOS device and fabricating method thereof |
November 10, 2009 |
| A CMOS device is provided, comprising a substrate, a first-type MOS transistor, a second-type MOS transistor, a first stress layer, a first liner layer, and a second stress layer. The substrate has a first active area and a second active area, which are separated by an isolation stru |
| 7615399 |
Fabrication method of complementary metal oxide semiconductor image sensor |
November 10, 2009 |
| A fabrication method of a CMOS image sensor including a light-receiving element, at least one transistor, a first dielectric layer, a reflective layer, a second dielectric layer, a protective layer, a material layer, a transparent material layer, an optical filter, and a converging eleme |
| 7608522 |
Method for fabricating a hybrid orientation substrate |
October 27, 2009 |
| A method for fabricating a hybrid orientation substrate includes steps of providing a direct silicon bonding (DSB) wafer having a first substrate with (100) crystalline orientation and a second substrate with (110) crystalline orientation directly bonded on the first substrate, forming |
| 7608473 |
Image sensor device and manufacturing method thereof |
October 27, 2009 |
| An image sensor and a manufacturing method thereof are provided. The image sensor includes a plurality of sensors, an inter-layer dielectric layer formed over the sensors, a first inter-metal dielectric layer formed over the inter-layer dielectric layer, and a plurality of first via wall |
| 7606021 |
Metal-insulator-metal capacitor and method for fabricating the same |
October 20, 2009 |
| A metal-insulator-metal (MIM) capacitor that includes a silicon nitride (SiN) dielectric film is disclosed. The MIM capacitor includes a bottom electrode, a top electrode and a dielectric layer positioned between the bottom electrode and the top electrode. The dielectric layer includes a |
| 7602599 |
Metal-metal capacitor and method of making the same |
October 13, 2009 |
| A method of making a metal-metal capacitor is disclosed, in which a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, and a third metal layer are formed in the order over a substrate; an upper capacitor is defined by etching using a first mask, |
| 7602003 |
Semiconductor device structure for reducing hot carrier effect of MOS transistor |
October 13, 2009 |
| A semiconductor device structure is described, including a MOS transistor, a silicon-rich silicon nitride layer having a refractive index of about 2.00-2.30, and a dielectric layer. The silicon-rich silicon nitride layer is disposed between the MOS transistor and the dielectric layer, an |
| 7601587 |
Fabricating method of CMOS |
October 13, 2009 |
| A method of forming a metal-oxide-semiconductor (MOS) device is provided. The method includes the following steps. First, a conductive type MOS transistor is formed on a substrate. Then, a first etching stop layer is formed over the substrate to cover conformably the conductive type MOS |
| 7601404 |
Method for switching decoupled plasma nitridation processes of different doses |
October 13, 2009 |
| A method for switching decoupled plasma nitridation (DPN) processes of different doses, which is able to decrease the switching time, is provided. According to the method, a dummy wafer is inserted into a chamber, a process gas introduced is ignited into plasma, and then a DPN doping |
| 7598551 |
High voltage device |
October 6, 2009 |
| The invention is directed to a method for manufacturing a high voltage device. The method includes steps of providing a substrate and then forming a first doped region having a first conductive type in the substrate. At least two second doped regions having a second conductive type a |
| 7598023 |
Process for fabricating micro-display |
October 6, 2009 |
| A process for fabricating a micro-display is provided. First, a wafer having a driving circuit thereon is provided. Then, a metallic reflective layer is formed on the wafer. Thereafter, an anti-reflection layer and a patterned photoresist layer are sequentially formed on the metallic |
| 7596775 |
Method for determining a standard cell for IC design |
September 29, 2009 |
| IC design flow includes RTL design, synthesis, APR, and layout. An IC designer can choose a suitable standard cell for an integrated circuit according to the timing, area, and BCI (best cell index) of each standard cell. Further, the BCI of a standard cell can be generated by generating |
| 7595264 |
Fabrication method of semiconductor device |
September 29, 2009 |
| A method of fabricating a semiconductor device is provided. The method includes forming a refractory metal alloy layer over a silicon-containing conductive layer. The refractory metal alloy layer is constituted of a first refractory metal and a second refractory metal. Thereafter, a cap |
| 7595234 |
Fabricating method for a metal oxide semiconductor transistor |
September 29, 2009 |
| A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drai |
| 7592265 |
Method of trimming a hard mask layer, method for fabricating a gate in a MOS transistor, and a s |
September 22, 2009 |
| A method of trimming hard mask is provided. The method includes providing a substrate, a hard mask layer, and a tri-layer stack on the substrate. The tri-layer stack includes a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer. The top photo resist |
| 7592262 |
Method for manufacturing MOS transistors utilizing a hybrid hard mask |
September 22, 2009 |
| A method for manufacturing MOS transistor with hybrid hard mask includes providing a substrate having a dielectric layer and a polysilicon layer thereon, forming a hybrid hard mask having a middle hard mask and a spacer hard mask covering sidewalls of the middle hard mask on the poly |
| 7592231 |
MOS transistor and fabrication thereof |
September 22, 2009 |
| A method of fabricating a MOS transistor is described. A substrate is provided, and then a composite layer for forming a gate structure and a carbon-containing mask material layer are formed thereon in turn, wherein the carbon-containing mask material layer is formed with a carbon-co |
| 7589551 |
On-wafer AC stress test circuit |
September 15, 2009 |
| To make an alternating current (AC) stress test easier to perform in a wafer, an AC stress test circuit for performing the AC stress test on a test device fabricated in a test region of the wafer includes an oscillator module fabricated in the test region, a diode module fabricated i |
| 7589385 |
Semiconductor CMOS transistors and method of manufacturing the same |
September 15, 2009 |
| A CMOS transistor device including a tensile-stressed NMOS transistor and a PMOS transistor is disclosed. The NMOS transistor includes a gate, a gate oxide layer between the gate and semiconductor substrate, a silicon oxide offset spacer on sidewalls of the gate, N type lightly doped |
| 7589359 |
Silicon controlled rectifier |
September 15, 2009 |
| A silicon controlled rectifier structure with the symmetrical layout is provided. The N-type doped regions and the P-type doped regions are disposed with the N-well and symmetrically arranged relative to the isolation structure in-between, while the P-type buried layer is located und |
| 7588991 |
Method for fabricating embedded static random access memory |
September 15, 2009 |
| The present invention provides a method for fabricating an embedded static random access memory, including providing a semiconductor substrate; defining a logic area and a memory cell area on the semiconductor substrate and defining at least a first conductive device area and at leas |
| 7588883 |
Method for forming a gate and etching a conductive layer |
September 15, 2009 |
| A method for forming a gate and a method for etching a conductive layer are provided. First, a substrate is provided, including a dielectric layer and a conductive layer on its surface in order. Subsequently, a patterned silicon nitride layer is formed on the conductive layer as a ha |
| 7586721 |
ESD detection circuit |
September 8, 2009 |
| An ESD detection circuit which includes: a triggering circuit for generating an ESD trigger signal when the ESD detection circuit is in ESD mode; a bias circuit for providing at least a first bias voltage and a second bias voltage for controlling the operation of the triggering circu |
| 7586138 |
Image sensor and method of forming the same |
September 8, 2009 |
| An image sensor includes a semiconductor substrate, a photo receiving area in the semiconductor substrate, a gate electrode installed in a lateral side of the photo receiving area on the semiconductor substrate, and a patterned dielectric layer covering the gate electrode, the photo |
| 7585790 |
Method for forming semiconductor device |
September 8, 2009 |
| A method of forming a semiconductor device. The method comprises steps of providing a substrate having a first transistor, a second transistor and non-salicide device formed thereon and the conductive type of the first transistor is different from that of the second transistor. A buffer |
| 7582916 |
Silicon controlled rectifier |
September 1, 2009 |
| A silicon controlled rectifier structure of polygonal layouts is provided. The polygonal first conductive type doped region is located in the middle of the polygonal second conductive type well. The first conductive type well shaped as a polygonal ring surrounds the second conductive typ |
| 7582520 |
Method of fabricating complementary metal-oxide-semiconductor transistor and metal-oxide-semicon |
September 1, 2009 |
| A method of fabricating a metal-oxide-semiconductor transistor is provided. A first gate structure and a second gate structure are formed on a substrate. The first gate structure has a dimension greater than the second gate structure. Then, first lightly doped drain regions are formed |
| 7582212 |
Method of removing silicon dioxide from waste liquid, method of cleaning membrane tube and metho |
September 1, 2009 |
| A method of removing silicon dioxide from a waste liquid is described. A solution containing fluoride ions is added into the waste liquid to form a reaction product. A method of cleaning a membrane tube for processing waste water is also described, wherein the membrane tube contains |
| 7581331 |
Calibration device for nozzle and calibration method for nozzle |
September 1, 2009 |
| A calibration device for a nozzle suitable for calibrating a nozzle of a semiconductor apparatus is provided. The semiconductor apparatus includes a chuck with a center hole with radius R1. A cap with outer radius R3 is disposed outside the nozzle with outer radius R2. The calibration de |
| 7579913 |
Low power comsumption, low noise and high power gain distributed amplifiers for communication sy |
August 25, 2009 |
| Provided is a distributed amplifier in communication systems, including: an input transmission line; an output transmission line; an input impedance match and an output impedance match, for providing termination of the input transmission line and the output transmission line, respect |
| 7579250 |
Method for reducing hot carrier effect of MOS transistor |
August 25, 2009 |
| A semiconductor device structure is described, including a MOS transistor, a silicon-rich silicon nitride layer having a refractive index of about 2.00-2.30, and a dielectric layer. The silicon-rich silicon nitride layer is disposed between the MOS transistor and the dielectric layer, an |
| 7577418 |
Sub-harmonic mixer and down converter with the same |
August 18, 2009 |
| A sub-harmonic mixer and a down converter with the sub-harmonic mixer are provided. The sub-harmonic mixer includes a differential amplifying unit, a current buffer unit, and a switching unit. The differential amplifying unit is used to amplify a radio frequency (RF) signal and employs a |
| 7576013 |
Method of relieving wafer stress |
August 18, 2009 |
| A method of relieving wafer stress is provided. A wafer is provided, wherein at least a dielectric layer has already formed over the wafer and the wafer has a first and a second area. At least no circuits are formed on the dielectric layer within the first area. Thereafter, openings are |
| 7572722 |
Method of fabricating nickel silicide |
August 11, 2009 |
| A semiconductor device having nickel silicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer is formed on the semiconductor substrate, and a first rapid thermal process (RTP) is per |
| 7571415 |
Layout of power device |
August 4, 2009 |
| A layout of a power device is provided. The layout includes a substrate, a unit array, a plurality of first, second, third and fourth signal paths, and a first, second, third and fourth port. The unit array with a plurality of rows is disposed on the substrate. Each row of the unit a |
| 7569111 |
Method of cleaning deposition chamber |
August 4, 2009 |
| A process for cleaning a deposition chamber. The process includes feeding a fluorine-containing gas into the deposition chamber; maintaining the fluorine-containing gas in the deposition chamber at a first pressure; providing RF power to ignite plasma of the fluorine-containing gas withi |
| 7567319 |
LCoS display with a color pixel array with multiple reflective layers and fabrication method the |
July 28, 2009 |
| A method of fabricating an LCoS display with a color pixel array comprises a step of disposing reflective layers between various color filter layers. The reflective layers are used as etching stop layers between color filter layers so that etching processes are capable of defining pa |
| 7566932 |
Static random access memory unit |
July 28, 2009 |
| A static random access memory (SRAM) unit comprising a substrate, a gate dielectric layer, a gate, a trench capacitor, a pair of source/drain regions, a first contact and a second contact is provided. The substrate has a trench formed therein. The gate dielectric layer is disposed on the |
| 7566668 |
Method of forming contact |
July 28, 2009 |
| A method of forming a contact is provided. A substrate having at least two metal oxide semiconductor devices is provided and a gap is formed between the two devices. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate. The fi |
| 7566647 |
Method of disposing and arranging dummy patterns |
July 28, 2009 |
| A method of disposing dummy patterns is described, which is used for increasing the pattern density of an aluminum pad layer. A substrate is provided, and an aluminum pad material layer is formed on the substrate. Then, the aluminum pad material layer is patterned to form the aluminum |
| 7564083 |
Active pixel sensor |
July 21, 2009 |
| An active pixel sensor is proposed by the invention. The position of the gate of the reset transistor is kept away from the interface of the isolation region and the silicon so that the depletion region does not reach the isolation. Accordingly, dark currents caused by isolation regi |
| 7563671 |
Method for forming trench capacitor and memory cell |
July 21, 2009 |
| A method for forming a trench capacitor and memory cell by providing a substrate on which a grid STI and a plurality of active regions covered by a hard mask layer are formed. A photoresist is formed and a low grade photo mask having only X direction consideration is used to define the |
| 7562326 |
Method of generating a standard cell layout and transferring the standard cell layout to a subst |
July 14, 2009 |
| A method of generating a standard cell layout includes analyzing a circuit of a standard cell layout and obtaining an analysis result, selecting a plurality of leaf cell layout according to the analysis result, and piecing together the leaf cell layouts to generate the standard cell |
| 7560774 |
IC chip |
July 14, 2009 |
| An IC chip, including a switch LDMOS device and an analog LDMOS device, is configured on a substrate having a first conductive type. Components of the two LDMOS devices respectively include two gate conductive layers configured on two first active regions of the substrate. A common sourc |
| 7560356 |
Fabrication method of trench capacitor |
July 14, 2009 |
| A method of fabricating trench capacitors is provided. A plurality of trenches is formed in the substrate by performing a patterning process with a patterned mask layer on a substrate. A bottom electrode is formed in the substrate of the surface of the trench. A portion of the patterned |
