| Patent Number |
Title Of Patent |
Date Issued |
| RE35797 |
Logic array having high frequency internal clocking |
May 19, 1998 |
| A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state |
| 7453334 |
Leaky SAW resonator and method |
November 18, 2008 |
| A SAW ladder filter includes grating pads extending from opposing bus bars and interdigital transducer electrodes extending from the grating pads for defining an acoustic aperture. The metalization ratio for the grating pads is greater than that for the interdigital transducer electrodes |
| 7449728 |
Monolithic integrated enhancement mode and depletion mode field effect transistors and method of |
November 11, 2008 |
| A depletion mode (D-mode) field effect transistor (FET) is monolithically integrated with an enhancement mode (E-mode) FET in a multi-layer structure. The multi-layer structure includes a channel layer overlaid by a barrier layer overlaid by an ohmic contact layer. Source and drain c |
| 7385445 |
High efficiency amplifier circuits having bypass paths |
June 10, 2008 |
| Described herein are representative embodiments of amplifier bypass paths and amplifiers using such bypass paths. In certain exemplary embodiments, the amplifiers are operated as linear power amplifiers, such as may be used in wireless communications systems. According to one exemplary |
| 7382194 |
Switched distributed power amplifier |
June 3, 2008 |
| A switched distributed power amplifier includes an amplifier stage that includes a first amplifier subsection and a second amplifier subsection, both including one or more field effect transistors (FETs). Each FET in the first amplifier subsection is coupled to a radio frequency (RF) inp |
| 7382186 |
Amplifiers with high efficiency in multiple power modes |
June 3, 2008 |
| Described herein are representative embodiments of amplifiers having selectable power output while maintaining low power consumption. In certain exemplary embodiments, the amplifiers are operated as linear power amplifiers, such as may be used in wireless communication systems. Accor |
| 7368980 |
Producing reference voltages using transistors |
May 6, 2008 |
| An exemplary circuit embodiment includes a depletion-mode transistor and an enhancement-mode transistor. The circuit also includes a circuit portion coupled to a gate region of the depletion-mode transistor and to a gate region of the enhancement-mode transistor. In this embodiment, the |
| 7345537 |
Linear power amplifier with multiple output power levels |
March 18, 2008 |
| A power amplifier stage has a first amplifier subsection and a second amplifier subsection coupled in a parallel configuration. The first amplifier subsection receives a signal to be amplified and the second amplifier subsection receives the signal to be amplified via a first delay l |
| 7282997 |
Thermal coupling device |
October 16, 2007 |
| A micro-electronic power amplifier that defines a uniform thermal impedance includes an output stage including a single transistor array including a plurality of emitter leads and a single thermal coupling device that thermally couples together each of the emitter leads. |
| 7276777 |
Thin film resistor and method of making the same |
October 2, 2007 |
| One embodiment of an integrated circuit includes a substrate and a SiWNi thin film resistor formed on the substrate. |
| 7263337 |
Circuit for boosting DC voltage |
August 28, 2007 |
| A bias circuit that includes a rectifier having an input, an output and a DC control voltage input, wherein the rectifier is configured to produce the rectifier output, while providing a substantially high input impedance at the rectifier input, a rectified voltage from an alternating |
| 7250673 |
Signal isolation in a package substrate |
July 31, 2007 |
| Signal traces are patterned on a top surface of a substrate. A ground trace is patterned on the top surface of the substrate for at least one pair of the signal traces. A die paddle is patterned on the top surface of the substrate, and the die paddle is connected directly with the gr |
| 7230492 |
Robust monolithic automatic bias circuit with current setting apparatus |
June 12, 2007 |
| A bias circuit includes a regulator circuit and a current diverting circuit. The regulator circuit includes a load resistor, a first transistor, and feedback control circuitry for biasing the first transistor such that a nominal quiescent current flows through the first resistor and |
| 7224230 |
Bias circuit with mode control and compensation for voltage and temperature |
May 29, 2007 |
| An amplifier bias system. The amplifier bias system includes a battery voltage supply coupled with an amplifier transistor to be biased; an output node coupled with a gate of the amplifier transistor; and a current source coupled with the battery voltage supply, wherein the current s |
| 7177370 |
Method and architecture for dual-mode linear and saturated power amplifier operation |
February 13, 2007 |
| An RF transmitter provides both GSM and EDGE capability by implementing collector voltage control over the power transistor(s) in a power amplifier. During EDGE mode, linear base-biasing a power amplifier (PA) allows collector control to provide either saturated mode PA operation (du |
| 7164319 |
Power amplifier with multi mode gain circuit |
January 16, 2007 |
| A power amplifier comprises an input terminal, an output terminal and a first amplification stage coupled with the input and output terminals. The first amplification stage having a node and a resistive structure coupled with the node. The resistive structure includes a first resistive |
| 7148748 |
Active protection circuit for load mismatched power amplifier |
December 12, 2006 |
| A peak detector detects an amplifier output overvoltage condition if the amplifier drives a mismatched load impedance. In response to the detected overvoltage condition, a clamping transistor lowers a reference DC bias voltage supplied by a bias circuit to the amplifier. The lowered |
| 7148463 |
Increased responsivity photodetector |
December 12, 2006 |
| A photodetector includes a high-indium-concentration (H-I-C) absorption layer having a Group III sublattice indium concentration greater than 53%. The H-I-C absorption layer improves responsivity without decreasing bandwidth. The photoconversion structure that includes the H-I-C abso |
| 7138889 |
Single-port multi-resonator acoustic resonator device |
November 21, 2006 |
| A single port multi-resonator acoustic resonator device (200, 300, 400, 490) possesses an input impedance that exhibits precisely designed electrical resonances. The device contains at least three parts: a transducer/resonator (201, 301, 401. 491) used both to interface to an externa |
| 7130124 |
Average pitch gratings for optical filtering applications |
October 31, 2006 |
| A pitch averaging Bragg grating includes a plurality of grating peaks spaced by different pitch values. By selecting the different pitch values to have an average pitch value equal to a target pitch value, the pitch averaging Bragg grating can be made to perform like a constant pitch |
| 7102464 |
Switched transformer for adjusting power amplifier loading |
September 5, 2006 |
| A circuit includes a transmission line transformer coupled between an input and output port. An inductor may be selectively coupled into the ground return path of the transmission line transformer to alter the impedance transformation provided between the input and output ports. |
| 7046083 |
Efficient power control of a power amplifier by periphery switching |
May 16, 2006 |
| A power amplifier having a first amplifier output stage and a parallel second amplifier output stage is provided. The first amplifier output stage is enabled (i.e., fully biased) during both high power and low power operating modes. The second amplifier output stage is disabled durin |
| 7010284 |
Wireless communications device including power detector circuit coupled to sample signal at inte |
March 7, 2006 |
| A multi-stage amplifier is coupled with a power detector. The multi-stage amplifier includes a plurality of amplifier stages in series, with a signal path extending through them. The power detector is coupled to an interior node of the amplifier along the signal path, and is operable to |
| 6998320 |
Passivation layer for group III-V semiconductor devices |
February 14, 2006 |
| A passivation layer for a heterojunction bipolar transistor (HBT) is formed from a relatively high bandgap material that is lattice-matched to the HBT components it passivates. By selecting the passivation layer to have a higher bandgap than the HBT components, minority carriers are |
| 6989712 |
Accurate power detection for a multi-stage amplifier |
January 24, 2006 |
| A multi-stage amplifier is coupled with a power detector. The multi-stage amplifier includes a plurality of amplifier stages in series, with a signal path extending through them. The power detector is coupled to an interior node of the amplifier along the signal path, and is operable to |
| 6930555 |
Amplifier power control circuit |
August 16, 2005 |
| A sense transistor is placed in a current path between a reference voltage source and ground. The base terminal of the sense transistor is coupled to the base terminal of an amplifying transistor. Thus, current in the sense transistor corresponds to signal power output by the amplifying |
| 6894561 |
Efficient power control of a power amplifier by periphery switching |
May 17, 2005 |
| A power amplifier having a first amplifier output stage and a parallel second amplifier output stage is provided. The first amplifier output stage is enabled (i.e., fully biased) during both high power and low power operating modes. The second amplifier output stage is disabled during th |
| 6882240 |
Integrated segmented and interdigitated broadside- and edge-coupled transmission lines |
April 19, 2005 |
| A transmission line element is formed in an integrated circuit chip. The transmission line element includes a plurality of parallel conductors, with each conductor including a plurality of electrically connected transmission lines. At least two of the transmission lines of each condu |
| 6879214 |
Bias circuit with controlled temperature dependence |
April 12, 2005 |
| A bias control circuit generates a bias control current that is proportional to temperature. The bias control current is drawn from a first node of a bias circuit. The first node of the bias circuit is also configured to receive a relatively large first current that is also proportio |
| 6853250 |
Amplifier power control circuit |
February 8, 2005 |
| A sense transistor is placed in a current path between a reference voltage source and ground. The base terminal of the sense transistor is coupled to the base terminal of an amplifying transistor. Thus, current in the sense transistor corresponds to signal power output by the amplifying |
| 6806558 |
Integrated segmented and interdigitated broadside- and edge-coupled transmission lines |
October 19, 2004 |
| A combination edge- and broadside-coupled transmission line element formed in an integrated circuit chip, using semiconductor processes, in a stack of metal layers separated by dielectric layers. Each of the metal layers includes a number of transmission lines. Interconnects between the |
| 6787826 |
Heterostructure field effect transistor |
September 7, 2004 |
| A high electron mobility transistor is constructed with a substrate, a lattice-matching buffer layer formed on the substrate, and a heavily doped p-type barrier layer formed on the buffer layer. A spacer layer is formed on the barrier layer, and a channel layer is formed on the spacer la |
| 6762647 |
Active protection circuit for load mismatched power amplifier |
July 13, 2004 |
| A peak detector detects an amplifier output overvoltage condition if the amplifier drives a mismatched load impedance. In response to the detected overvoltage condition, a clamping transistor lowers a reference DC bias voltage supplied by a bias circuit to the amplifier. The lowered refe |
| 6727761 |
Resonant bypassed base ballast circuit |
April 27, 2004 |
| Base ballast resistors used to control thermal runaway are each bypassed with a series-resonant inductor and capacitor pair. In some embodiments each inductor and capacitor pair is unique. In other embodiments a common inductor is used for each inductor and capacitor pair. |
| 6697412 |
Long wavelength laser diodes on metamorphic buffer modified gallium arsenide wafers |
February 24, 2004 |
| A light-emitting device includes a GaAs substrate, a light-emitting structure disposed above the substrate and capable of emitting light having a wavelength of about 1.3 microns to about 1.55 microns, and a buffer layer disposed between the substrate and the light-emitting structure. |
| 6653902 |
Amplifier power control circuit |
November 25, 2003 |
| A sense transistor is placed in a current path between a reference voltage source and ground. The base terminal of the sense transistor is coupled to the base terminal of an amplifying transistor. Thus, current in the sense transistor corresponds to signal power output by the amplifying |
| 6535532 |
Method and apparatus to select optimal operating conditions in a digital wavelength stabilized c |
March 18, 2003 |
| A method for controlling tuning current values provided to a multichannel laser source. For each operating laser channel, a desired slope value of laser power as a function of tuning current is stored. The slope values of laser power as a function of tuning current is then measured. The |
| 6529079 |
RF power amplifier with distributed bias circuit |
March 4, 2003 |
| An improved amplifier circuit is disclosed. In one embodiment, the amplifier circuit includes an amplifier transistor that has a base terminal connected to receive an input signal. The amplifier circuit also includes a reference voltage source that generates a reference voltage at a |
| 6459340 |
Power amplifier mismatch protection with clamping diodes in RF feedback circuit |
October 1, 2002 |
| A set of clamping diodes between terminals of a transistor acting as a power amplifier is configured to allow overvoltage at the output terminal of the transistor to travel through those clamping diodes to provide feedback used by the transistor for gain control. |
| 6441687 |
Amplifier bias voltage generating circuit and method |
August 27, 2002 |
| A novel bias voltage generating circuit and method are disclosed. In one embodiment, the bias voltage generating circuit includes a first transistor with a base terminal coupled to the output node and an emitter terminal coupled to ground. The circuit also includes a resistor with a |
| 6437658 |
Three-level semiconductor balun and method for creating the same |
August 20, 2002 |
| A three-level semiconductor balun is disclosed. In one embodiment, the balun includes a first spiral-shaped transmission line overlying a substrate. The first transmission line has first and second ends. A second spiral-shaped transmission line is substantially vertically aligned with |
| 6437628 |
Differential level shifting buffer |
August 20, 2002 |
| A buffer includes two pairs of push-pull configured transistors as output drivers. One transistor in the first push-pull pair is controlled by an input signal and the second transistor in the first push-pull pair is controlled via a current mirror by a complement of the input signal. |
| 6407647 |
Integrated broadside coupled transmission line element |
June 18, 2002 |
| A novel broadside-coupled transmission line element is disclosed. The element includes a first metallization layer that has a first spiral-shaped transmission line and at least one bridge segment formed therein. The element also includes a second metallization layer that has a second |
| 6404296 |
Amplitude-leveled wide-range source-coupled oscillator |
June 11, 2002 |
| A source-coupled oscillator contains two main MESFETs which supply current to respective loads and which have sources connected through a capacitor. Each of the main MESFETs is supplied with a constant current which can be adjusted to vary the frequency of the oscillator. The output sign |
| 6310509 |
Differential multiplexer with high bandwidth and reduced crosstalk |
October 30, 2001 |
| A multiplexer includes a first input device that receives a first input signal and a first select signal. When the first select signal has a first state, the first input device generates a first voltage at a first node in response to the first input signal. When the first select signal h |
| 6265756 |
Electrostatic discharge protection device |
July 24, 2001 |
| An electrostatic discharge protection device for reducing electrostatic discharge spikes on a signal line is disclosed. The electrostatic discharge protection device includes first and second contact regions formed in a semiconductor material such as a compound semiconductor substrat |
| 6233440 |
RF power amplifier with variable bias current |
May 15, 2001 |
| An RF power amplifier with variable bias current is disclosed. The RF amplifier includes a peak detector that detects the peak level of the amplifier input signal. The peak detector generates an output signal in response to the peak level of the amplifier input signal. A bias voltage |
| 6148220 |
Battery life extending technique for mobile wireless applications |
November 14, 2000 |
| An operating voltage applied to a transmitter's power amplifier in a mobile wireless transceiver is dynamically controlled so as to improve the efficiency of the transmitter at all output power levels. In one embodiment, the bias current levels within the transmitter are also varied |
| 6124734 |
High-speed push-pull output stage for logic circuits |
September 26, 2000 |
| A logic circuit output stage includes a first transistor with a first terminal that receives the first logic output signal and a third terminal coupled to a first output node. A second transistor has a first terminal coupled to the first terminal of the first transistor. A third transist |
| 6078505 |
Circuit board assembly method |
June 20, 2000 |
| A method is disclosed for attaching a device package to a circuit board with a chip mount area that has a set of elongated pads located near the perimeter of a chip mount area. In accordance with this method, a mask is formed on the circuit board. A plurality of openings are formed in th |
