| Patent Number |
Title Of Patent |
Date Issued |
| 7439575 |
Protection against in-process charging in silicon-oxide-nitride-oxide-silicon (SONOS) memories |
October 21, 2008 |
| A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric |
| 7400538 |
NROM memory device with enhanced endurance |
July 15, 2008 |
| The efficient removal of parasitic electron charges from the ONO structure of an NROM cell by periodically applying a negative gate refresh voltage in a way that injects holes from the substrate into the ONO structure. Initially, after each erase pulse is generated and an unacceptable er |
| 7397088 |
Electrostatic discharge protection device for radio frequency applications based on an isolated |
July 8, 2008 |
| A lateral bipolar transistor is used to protect a passive radio frequency (RF) microelectronic circuit during electrostatic discharge (ESD) events. The microelectronic circuit receives a high frequency differential input signal across first and second pads. The lateral bipolar transistor |
| 7368760 |
Low parasitic capacitance Schottky diode |
May 6, 2008 |
| A low parasitic capacitance Schottky diode including a lightly doped polycrystalline silicon island that is formed on a shallow trench isolation (STI) pad such that the polycrystalline silicon island is entirely isolated from an underlying silicon substrate by the STI pad. The result |
| 7358583 |
Via wave guide with curved light concentrator for image sensing devices |
April 15, 2008 |
| A CMOS image sensor (CIS) device includes an array of pixels, each pixel including a sensing element (e.g., a photodiode) and access circuitry. To facilitate the passage of light to the photodiode, each pixel includes a via wave guide (VWG) defined in the metallization layer formed over |
| 7339829 |
Ultra low power non-volatile memory module |
March 4, 2008 |
| An improved ultra-low power NVM module, which exhibits low power consumption and reduced layout area. An array of compact flash memory cells are programmed and erased in response to positive and negative boosted voltages. However, the compact flash memory cells are read using convent |
| 7313649 |
Flash memory and program verify method for flash memory |
December 25, 2007 |
| In conventional memory arrays in which a bit line is shared by memory cells, a cell current flows over into neighbor cell(s) in a program verify process, and therefore, the threshold of a memory cell to be programmed is erroneously determined to be lower. Therefore, in a program veri |
| 7280405 |
Integrator-based current sensing circuit for reading memory cells |
October 9, 2007 |
| Near-ground sensing of non-volatile memory (NVM) cells is performed on a selected NVM cell by applying a potential to a first terminal, coupling a second terminal to ground, and then decoupling the second terminal and passing the resulting cell current to an integrator, which generates a |
| 7227234 |
Embedded non-volatile memory cell with charge-trapping sidewall spacers |
June 5, 2007 |
| An IC includes both "volatile" CMOS transistors (FETs) and embedded non-volatile memory (NVM) cells, both including polysilicon gate structures, sidewall oxide layers, sidewall spacer structures, and source/drain regions. The sidewall spacers of both the NVM cells and the FETs are ma |
| 7172922 |
CMOS image sensor array with black pixel using negative-tone resist support layer |
February 6, 2007 |
| A "black" pixel for measuring dark current is produced using carbon-based or pigment-based black photosensitive resist deposited on a support layer that is formed using negative-tone photosensitive resist, both being formed over the light sensitive portion of the black pixel. After an |
| 7060627 |
Method of decreasing charging effects in oxide-nitride-oxide (ONO) memory arrays |
June 13, 2006 |
| A fieldless array includes a semiconductor substrate, a plurality of oxide-nitride-oxide (ONO) structures formed over the upper surface of the semiconductor substrate, and a plurality of word lines formed over the ONO structures, wherein each of the ONO structures is substantially co |
| 7016225 |
Four-bit non-volatile memory transistor and array |
March 21, 2006 |
| A non-volatile memory cell capable of storing more than two bits of information. The NVM cell includes a semiconductor region having a first conductivity type, and a plurality of field isolation regions located in the semiconductor region. Four or more source/drain regions are located |
| 6981188 |
Non-volatile memory device with self test |
December 27, 2005 |
| Self-test instructions are loaded from a tester into a configuration array of a memory device, and then a control circuit of the memory device sequentially reads and executes the self-test instructions while the tester is in an idle state. Data patterns are written to a main memory a |
| 6959920 |
Protection against in-process charging in silicon-oxide-nitride-oxide-silicon (SONOS) memories |
November 1, 2005 |
| A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric |
| 6956771 |
Voltage control circuit for high voltage supply |
October 18, 2005 |
| A voltage control circuit that utilizes a level-shifter circuit and a switch circuit to isolate a charge pump output terminal from a system voltage source when a charge pump is enabled, and to couple the charge pump output terminal to the system voltage source when the charge pump is |
| 6937523 |
Neighbor effect cancellation in memory array architecture |
August 30, 2005 |
| Non-volatile memory (NVM) cells are sensed using a forced neighbor signal to eliminate improper readings generated by a neighbor effect. A selected NVM cell is sensed using a near-ground signal by applying a potential to a first terminal, coupling a second terminal to ground, and then de |
| 6878981 |
Triple-well charge pump stage with no threshold voltage back-bias effect |
April 12, 2005 |
| A charge pump stage includes a first n-channel transistor having a source coupled to an input terminal and a drain coupled to an output terminal. A second n-channel transistor has a source coupled to the input terminal, a drain coupled to a gate of the first transistor, and a gate couple |
| 6871307 |
Efficient test structure for non-volatile memory and other semiconductor integrated circuits |
March 22, 2005 |
| A test system includes a test wafer having non-volatile memory dies and an exposed set of pads. A probe wafer includes test circuitry, a first set of pads exposed at a first surface, a second set of pads exposed at a second surface (opposite the first surface), and an interconnect struct |
| 6836443 |
Apparatus and method of high speed current sensing for low voltage operation |
December 28, 2004 |
| A sensing system for a memory cell in a memory array includes a current integrator circuit configured to integrate a read current through the memory cell and a reference current through a reference memory cell. The integration process creates a set of differential measurement voltages |
| 6809948 |
Mask programmable read-only memory (ROM) cell |
October 26, 2004 |
| A multi-bit programmable memory cell is provided that includes an access transistor and a plurality of N anti-fuse elements. The access transistor has a source coupled to a source line and a gate coupled to a word line. Each of the anti-fuse elements has a first terminal coupled to a dra |
| 6788576 |
Complementary non-volatile memory cell |
September 7, 2004 |
| A complimentary non-volatile memory (CNVM) cell includes an n-channel transistor and a p-channel transistor that have drains connected like a CMOS inverter, and that are controlled by a shared floating gate and a shared control gate. The CNVM cell is programmed by band-to-band tunneling |
| 6775186 |
Low voltage sensing circuit for non-volatile memory device |
August 10, 2004 |
| Low voltage sensing circuits for non-volatile memory (NVM) devices including a comparator (operational amplifier) having input terminals connected to the gate terminals of first and second PMOS transistors. The PMOS transistors are coupled between a system voltage source and respecti |
| 6774704 |
Control circuit for selecting the greater of two voltage signals |
August 10, 2004 |
| A voltage control circuit for a non-volatile memory (NVM) array or other integrated circuit that uses a comparator circuit, a switch control circuit, and a pair of PMOS switches to selectively couple an output node to the greater of two voltage signals. An output gain provided by the |
| 6765259 |
Non-volatile memory transistor array implementing "H" shaped source/drain regions and method for |
July 20, 2004 |
| A non-volatile memory (NVM) array including a plurality of 2-bit NVM transistors arranged in a plurality of rows extending along a first axis, and a plurality of columns extending along a second axis, perpendicular to the first axis. The non-volatile memory array includes a plurality of |
| 6703298 |
Self-aligned process for fabricating memory cells with two isolated floating gates |
March 9, 2004 |
| A self-aligned process for fabricating a non-volatile memory cell having two isolated floating gates. The process includes forming a gate dielectric layer over a semiconductor substrate. A floating gate layer is then formed over the gate dielectric layer. A disposable layer is formed |
| 6686276 |
Semiconductor chip having both polycide and salicide gates and methods for making same |
February 3, 2004 |
| A semiconductor process is provided that creates transistors having polycide gates in a first region of a semiconductor substrate and transistors having salicide gates in a second region of the semiconductor substrate. A polysilicon layer having a first portion in the first region an |
| 6617174 |
Fieldless CMOS image sensor |
September 9, 2003 |
| A fieldless CMOS image sensor that include a non-LOCOS isolation structure surrounding the photodiode diffusion region of each pixel. The isolation structure is formed by an anti-punchthrough (APT) implant isolation region formed in the substrate around the photodiode diffusion region, a |
| 6611456 |
Method and apparatus for reducing the number of programmed bits in a memory array |
August 26, 2003 |
| A memory system that reduces the number of memory cells programmed in a memory array is provided. A logic comparator determines whether more than half of the bits of a write data word require a program operation. If so, the logic comparator provides a status signal having a first state. |
| 6590797 |
Multi-bit programmable memory cell having multiple anti-fuse elements |
July 8, 2003 |
| A multi-bit programmable memory cell is provided that includes an access transistor and a plurality of N anti-fuse elements. The access transistor has a source coupled to a source line and a gate coupled to a word line. Each of the anti-fuse elements has a first terminal coupled to a dra |
| 6583066 |
Methods for fabricating a semiconductor chip having CMOS devices and fieldless array |
June 24, 2003 |
| A method for etching an oxide-nitride-oxide (ONO) layer fabricated on a semiconductor wafer, the ONO layer including a lower oxide layer, a nitride layer located over the lower oxide layer, and an upper oxide layer located over the nitride layer. The method includes the steps of removing |
| 6532176 |
Non-volatile memory array with equalized bit line potentials |
March 11, 2003 |
| A non-volatile memory (NVM) system that includes an array of NVM cells arranged in rows and columns and an equalization control circuit is provided. One row of the array forms a row of equalization NVM cells. Each of the equalization NVM cells is erased, such that these cells exhibit a |
| 6466079 |
High voltage charge pump for providing output voltage close to maximum high voltage of a CMOS de |
October 15, 2002 |
| An output stage for a charge pump is provided that includes a first PMOS transistor, a second PMOS transistor, a pull-down transistor and a capacitor. The first PMOS transistor includes a source and a bulk region coupled to receive a charging signal, a drain coupled to a first node, and |
| 6459620 |
Sense amplifier offset cancellation in non-volatile memory circuits by dedicated programmed refe |
October 1, 2002 |
| A non-volatile memory (NVM) system including an array of NVM cells, a column decoder, a set of comparators and a corresponding set of NVM reference blocks is provided. During a read operation, the column decoder routes a set of read output voltages from an addressed set of the NVM ce |
| 6458702 |
Methods for making semiconductor chip having both self aligned silicide regions and non-self ali |
October 1, 2002 |
| A semiconductor process is provided that creates fully-salicided transistors. in a first region and partially-salicided transistors in a second region. Each of the fully-salicided transistors includes a salicided gate electrode and salicided active regions. Each of the partially-sali |
| 6456557 |
Voltage regulator for memory device |
September 24, 2002 |
| A memory device includes a voltage regulator that compensates for resistance variations in the bit line control (multiplexing) circuit used to access the memory cells by including in its feedback path an emulated multiplexing circuit having an identical resistance to that of the mult |
| 6448822 |
Comparator for negative and near-ground signals |
September 10, 2002 |
| A comparator circuit that transforms a difference between two input voltage signals into differential branch currents that are independent of the two input voltage signals. In one embodiment, the comparator circuit utilizes an adaptive bias voltage circuit and a cascode stage to generate |
| 6421276 |
Method and apparatus for controlling erase operations of a non-volatile memory system |
July 16, 2002 |
| A non-volatile memory system having an array of 2-bit cells is provided, wherein each cell stores an odd bit and an even bit. An ERASE pulse is applied to either the odd bits or the even bits in response to an ODD_EVEN control signal, which toggles in response to an ERASE pulse. A first |
| 6362508 |
Triple layer pre-metal dielectric structure for CMOS memory devices |
March 26, 2002 |
| A CMOS memory device includes source and drain regions diffused into a substrate, a polysilicon gate structure formed over a channel region located between the first and second diffusion regions, and a pre-metal dielectric structure formed over the polysilicon gate structure. The pre |
| 6362498 |
Color image sensor with embedded microlens array |
March 26, 2002 |
| A color CMOS image sensor including a matrix of pixels (e.g., CMOS APS cells) that are fabricated on a semiconductor substrate. A silicon-nitride layer is deposited on the upper surface of the pixels, and is etched using a reactive ion etching (RIE) process to form microlenses. A protect |
| 6351415 |
Symmetrical non-volatile memory array architecture without neighbor effect |
February 26, 2002 |
| A method is provided for reading a first non-volatile memory transistor in an array of non-volatile memory transistors, wherein the first non-volatile memory transistor has a drain coupled to a source of a neighbor non-volatile memory transistor. The method includes the steps of (1) |
| 6346442 |
Methods for fabricating a semiconductor chip having CMOS devices and a fieldless array |
February 12, 2002 |
| A fieldless array of floating gate transistors is fabricated by forming an oxide-nitride-oxide (ONO) layer over a semiconductor substrate. A mask is formed over the ONO layer, the mask having openings that define a plurality of bit line regions of the floating gate transistors in the |
| 6340620 |
Method of fabricating a capacitor |
January 22, 2002 |
| A process for fabricating a capacitor in a microcircuit, and the capacitor so fabricated. A first layer of a polycrystalline semiconductor, preferably polysilicon, is deposited. A layer of a binary metallic conductor, preferably tungsten silicide, is deposited on the first layer of p |
| 6339540 |
Content-addressable memory for virtual ground flash architectures |
January 15, 2002 |
| Five architectures for the implementation of virtual ground non-volatile content-addressable memory are provided. Three of the architectures are applicable to 2-bit non-volatile memory transistors having separate programming capability for two current directions (i.e., drain-to-source |
| 6329691 |
Device for protection of sensitive gate dielectrics of advanced non-volatile memory devices from |
December 11, 2001 |
| A protective circuit includes a pair of diodes to protect the gate dielectric of an insulated-gate semiconductor device from over-voltage conditions, such as can occur during plasma etch manufacturing processes. The diodes are either anode- or cathode-coupled, and are connected between |
| 6297984 |
Structure and method for protecting integrated circuits during plasma processing |
October 2, 2001 |
| A protection circuit and method for preventing high word line voltages during plasma processing of integrated circuits. The protection circuit includes a shunt transistor connected between each word line and ground, and a light sensitive element connected to the gate of each shunt tr |
| 6295595 |
Method and structure for accessing a reduced address space of a defective memory |
September 25, 2001 |
| A circuit and method for producing defect tolerant high density memory cells at a low cost is disclosed. Rather than using redundant memory cells to salvage a memory circuit having non-functional memory cells, an address mapping circuit is used to remap addresses for non-functional memor |
| 6288434 |
Photodetecting integrated circuits with low cross talk |
September 11, 2001 |
| An anti-reflective layer is formed on the sidewalls of metal interconnects in an integrated circuit containing photodetector devices. After fabricating the photodetector devices, the metal interconnects are formed. An anti-reflective layer is formed over the interconnects and is dire |
| 6285065 |
Color filters formed on integrated circuits |
September 4, 2001 |
| Light transmitting filter elements are formed in holes etched in a covering passivation layer overlying light sensing devices formed in an integrated circuit. Filter material is spun on to the wafer to fill the etched holes. The filter material is cured and etched back below the passivat |
| 6256231 |
EEPROM array using 2-bit non-volatile memory cells and method of implementing same |
July 3, 2001 |
| A structure and method for implementing an EEPROM using 2-bit non-volatile memory cells. Each memory cell has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. The memory cells are arranged in one or more rows, with a wor |
| 6242345 |
Batch process for forming metal plugs in a dielectric layer of a semiconductor wafer |
June 5, 2001 |
| A batch process for the high-pressure forming of metal plugs in the dielectric layers of semiconductor wafers. After holes are etched in the dielectric layer of each wafer, and a layer of a metal such as aluminum deposited over the dielectric, both the etching and the deposition being |
