| Patent Number |
Title Of Patent |
Date Issued |
| 7444525 |
Methods and apparatus for reducing leakage current in a disabled SOI circuit |
October 28, 2008 |
| Methods and apparatus provide for enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital |
| 7402885 |
LOCOS on SOI and HOT semiconductor device and method for manufacturing |
July 22, 2008 |
| One or more local oxidation of silicon (LOCOS) regions may be formed that apply compressive strain to a channel of a field-effect transistor such as a P-type field-effect transistor (PFET) or other circuit element of a semiconductor device. For instance, a pair of LOCOS regions may be fo |
| 7373447 |
Multi-port processor architecture with bidirectional interfaces between busses |
May 13, 2008 |
| A multi-port processor architecture having a first bus, a second bus and a central processing unit. The central processing unit having a first and second ports coupled to first and second busses respectively. A first bus to second bus bi-directional interface couples the first bus to the |
| 7285995 |
Charge pump |
October 23, 2007 |
| A charge pump that employs a differential amplifier that provides a differential output to control a charge up current source and a charge down current source. The differential amplifier is configured so that the current sources can maintain substantially equal charge up current and |
| 7272181 |
Method and apparatus for estimating and controlling the number of bits output from a video coder |
September 18, 2007 |
| A method and apparatus is provided for estimating the number of bits output from a video coder given a known spatial data content, G={g.sub.1, . . . , g.sub.N}, of a group of luminance and chrominance blocks, and a known coding mode, d, where d represents the index of said coding mode. |
| 7271751 |
Digital BIST test scheme for ADC/DAC circuits |
September 18, 2007 |
| A generalized method for testing DACs (Digital to Analog Converters) and ADCs (Analog to Digital Converters), such as Sigma Delta (Successive Approximation), Pipeline or Flash ADCs. The DACs and ADCs are tested in pairs using a Digital Tester and on chip test circuitry. The DACs and |
| 7257703 |
Bootable NAND flash memory architecture |
August 14, 2007 |
| A memory architecture allows for use of non-addressable NAND memory to be used as boot memory in digital processing systems. NAND memory, which is typically of lower cost and higher density, may displace all memory in processor systems, as particularly useful in low-power processor i |
| 7236057 |
Spread spectrum clock generator |
June 26, 2007 |
| A clock signal generator varies a frequency of a digital clock over a selected range of frequencies. The generator employs a divider for lowering a frequency of a clock signal. A counter increments synchronously with the signal, and causes a selected sequence of outputs to be generat |
| 7227426 |
Using hysteresis to generate a low power clock |
June 5, 2007 |
| A real time clock that operates an oscillator within a predetermined range by employing a constant current source. The remaining real time clock logic can be operated at a voltage that is relative to the constant current. Power consumption of the oscillator can be controlled by limit |
| 7151399 |
System and method for generating multiple clock signals |
December 19, 2006 |
| A technique for generating multiple clock signals using a frequency generator for generating a common clock signal. A first digital divider and multiplier receives the common clock signal and produces a first clock signal. A second digital divider and multiplier receives the common c |
| 7107376 |
Systems and methods for bandwidth shaping |
September 12, 2006 |
| Systems and methods for controlling access by a set of agents to a resource, where the agents have corresponding priorities associated with them, and where a monitor associated with the resource controls accesses by the agents to the resource based on the priorities. One embodiment is |
| 6963227 |
Apparatus and method for precharging and discharging a domino circuit |
November 8, 2005 |
| A domino circuit configuration includes a precharge transistor coupled to a discharge transistor, wherein the precharge transistor and the discharge transistor are not on simultaneously. |
| 6927635 |
Lock detectors having a narrow sensitivity range |
August 9, 2005 |
| Lock detectors are provided that have a narrow sensitivity range. |
| 6833736 |
Pulse generating circuit |
December 21, 2004 |
| A pulse generator circuit includes a first logic means, a second logic means, a first delay means, and a second delay means. The first logic means is for receiving an input clock signal. The first delay means is for delaying the input clock signal by a first delay time. The second logic |
| 6639942 |
Method and apparatus for estimating and controlling the number of bits |
October 28, 2003 |
| A method and apparatus is provided for estimating the number of bits output from a video coder given a known spatial data content, G={g.sub.1, . . . ,g.sub.N }, of a group of luminance and chrominance blocks, and a known coding mode, d, where d represents the index of coding mode. The me |
| 6185649 |
System for correcting an illegal addressing signal by changing a current bit from one to zero if |
February 6, 2001 |
| An apparatus and a method detect and automatically correct an illegal address in a peripheral connect interface bus addressing scheme. The value of a current bit is read. The value of a bit immediately left adjacent of the current bit is read. A value of 0 is outputted as the current bit |
| 6067267 |
Four-way interleaved FIFO architecture with look ahead conditional decoder for PCI applications |
May 23, 2000 |
| A FIFO memory apparatus of the present invention includes an array of registers including a plurality of stacked subarrays. A first plurality of multiplexers is provided including one multiplexer for receiving data from each one of the subarrays. A second plurality of multiplexers is als |
| 6026141 |
One load conditional look ahead counter |
February 15, 2000 |
| A high modulus counter is provided for receiving a counter enable (CE) signal which switches between digital states. The counter is a single load conditional look ahead counter having a carry chain isolated from a timing critical path. The counter includes one toggle flip-flop for receiv |
| 5529953 |
Method of forming studs and interconnects in a multi-layered semiconductor device |
June 25, 1996 |
| A method of manufacturing a semiconductor device having a stud and interconnect in a dual damascene structure uses selective deposition. The method includes forming a trench including a first opening portion and a second opening portion in a dielectric layer, forming a first adhesion |
