| Patent Number |
Title Of Patent |
Date Issued |
| 6555872 |
Trench gate fermi-threshold field effect transistors |
April 29, 2003 |
| Field effect transistors include a semiconductor substrate of first conductivity type having a surface. A tub region of second conductivity type is in the semiconductor substrate at the surface and extends into the semiconductor substrate a first depth from the first surface. Spaced apar |
| 5885876 |
Methods of fabricating short channel fermi-threshold field effect transistors including drain fi |
March 23, 1999 |
| A Fermi-FET includes a drain field termination region between the source and drain regions, to reduce and preferably prevent injection of carriers from the source region into the channel as a result of drain bias. The drain field terminating region prevents excessive drain induced barrie |
| 5814869 |
Short channel fermi-threshold field effect transistors |
September 29, 1998 |
| A Fermi-threshold field effect transistor includes spaced-apart source and drain regions which extend beyond the Fermi-tub in the depth direction and which may also extend beyond the Fermi-tub in the lateral direction. In order to compensate for the junction with the substrate, the dopin |
| 5786620 |
Fermi-threshold field effect transistors including source/drain pocket implants and methods of f |
July 28, 1998 |
| A Fermi-FET, including but not limited to a tub-FET, a contoured-tub Fermi-FET or a short channel Fermi-FET includes a drain extension region of the same conductivity type as the drain region and a drain pocket implant region of opposite conductivity type from the drain region. The d |
| 5698884 |
Short channel fermi-threshold field effect transistors including drain field termination region |
December 16, 1997 |
| A Fermi-FET includes a drain field termination region between the source and drain regions, to reduce and preferably prevent injection of carriers from the source region into the channel as a result of drain bias. The drain field terminating region prevents excessive drain induced barrie |
| 5543654 |
Contoured-tub fermi-threshold field effect transistor and method of forming same |
August 6, 1996 |
| A Fermi-threshold field effect transistor includes a contoured-tub region of the same conductivity type as the source, drain and channel regions and having nonuniform tub depth. The contoured-tub is preferably deeper under the source and/or drain regions than under the channel region. Th |
| 5525822 |
Fermi threshold field effect transistor including doping gradient regions |
June 11, 1996 |
| A high saturation current, low leakage, Fermi threshold field effect transistor includes a predetermined minimum doping concentration of the source and drain facing the channel to maximize the saturation current of the transistor. Source and drain doping gradient regions between the |
| 5440160 |
High saturation current, low leakage current fermi threshold field effect transistor |
August 8, 1995 |
| A high saturation current, low leakage, Fermi threshold field effect transistor includes a predetermined minimum doping concentration of the source and drain facing the channel to maximize the saturation current of the transistor. Source and drain doping gradient regions between the |
| 5438007 |
Method of fabricating field effect transistor having polycrystalline silicon gate junction |
August 1, 1995 |
| A field effect transistor includes a polycrystalline silicon gate having a semiconductor junction therein. The semiconductor junction is formed of first and second oppositely doped polycrystalline silicon layers, and extends parallel to the substrate face. The polycrystalline silicon gat |
| 5424980 |
Self-timing random access memory |
June 13, 1995 |
| A random access memory (RAM) includes a plurality of sensing circuits. During a read operation, the RAM detects that one of the sensing circuits has sensed a binary digit. In response, the read operation is terminated and an idle operation is initiated to provide a self-timing RAM. Durin |
| 5396457 |
Random access memory including or gate sensing networks |
March 7, 1995 |
| A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inve |
| 5391949 |
Differential latching inverter circuit |
February 21, 1995 |
| A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inve |
| 5388075 |
Read and write timing system for random access memory |
February 7, 1995 |
| A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inve |
| 5384730 |
Coincident activation of pass transistors in a random access memory |
January 24, 1995 |
| The pass transistors in a random access memory array are activated only upon coincident (simultaneous) selection of both the associated row and the associated column of the memory cell; otherwise, activation of the pass transistors is prevented. Thus, when a word line is selected, only |
| 5374836 |
High current fermi threshold field effect transistor |
December 20, 1994 |
| A high current Fermi-FET includes an injector region of the same conductivity type as the Fermi-Tub region and the source and drain regions, located adjacent the source region and facing the drain region. The injector region is preferably doped at a doping level which is intermediate |
| 5371396 |
Field effect transistor having polycrystalline silicon gate junction |
December 6, 1994 |
| A field effect transistor includes a polycrystalline silicon gate having a semiconductor junction therein. The semiconductor junction is formed of first and second oppositely doped polycrystalline silicon layers, and extends parallel to the substrate face. The polycrystalline silicon gat |
| 5369295 |
Fermi threshold field effect transistor with reduced gate and diffusion capacitance |
November 29, 1994 |
| An improved Fermi FET structure with low gate and diffusion capacity allows conduction carriers to flow within the channel at a predetermined depth in the substrate below the gate, without requiring an inversion layer to be created at the surface of the semiconductor. The low capacity Fe |
| 5367186 |
Bounded tub fermi threshold field effect transistor |
November 22, 1994 |
| A Fermi-FET includes a Fermi-tub region at a semiconductor substrate surface, wherein the Fermi-tub depth is bounded between a maximum tub depth and a minimum tub depth. The Fermi-tub depth is sufficiently deep to completely deplete the Fermi-tub region by the substrate tub junction at |
| 5365483 |
Random access memory architecture including primary and signal bit lines and coupling means ther |
November 15, 1994 |
| A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inve |
| 5363001 |
Data input register for random access memory |
November 8, 1994 |
| A data input register for a random access memory includes a data input line which is coupled to TRUE and COMPLEMENT outputs. A first and a second Ring Segment Buffer is connected to a respective one of the TRUE and COMPLEMENT outputs. The Ring Segment Buffer produces TRUE and COMPLEMENT |
| 5357480 |
Address change detecting system for a memory |
October 18, 1994 |
| An address change detection system detects a change in an address input in a memory to initiate a read or write operation. The address change detection system uses a transition detection delay unit for each address bit of the memory. The transition detection delay unit is responsive to a |
| 5305269 |
Differential latching inverter and random access memory using same |
April 19, 1994 |
| A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inve |
| 5304874 |
Differential latching inverter and random access memory using same |
April 19, 1994 |
| A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inve |
| 5247212 |
Complementary logic input parallel (CLIP) logic circuit family |
September 21, 1993 |
| A high speed low Capacitance Complementary Logic Input Parallel (CLIP) logic family includes an FET driving stage, a complementary FET inverter, and at least one gating FET. The dimensions of the gating FET are controlled relative to the dimensions of the driving stage FETs to provide |
| 5222039 |
Static random access memory (SRAM) including Fermi-threshold field effect transistors |
June 22, 1993 |
| A static random access memory (SRAM) cell uses a pair of conventional cross-coupled MOSFET devices including an inversion layer, and a pair of inversion-free Fermi threshold FET devices, of the same conductivity type as the cross-coupled transistor pair, for resistive loads. The Fermi-FE |
| 5194923 |
Fermi threshold field effect transistor with reduced gate and diffusion capacitance |
March 16, 1993 |
| An improved Fermi FET structure with low gate and diffusion capacity allows conduction carriers to flow within the channel at a predetermined depth in the substrate below the gate, without requiring an inversion layer to be created at the surface of the semiconductor. The low capacity Fe |
| 5151759 |
Fermi threshold silicon-on-insulator field effect transistor |
September 29, 1992 |
| A Silicon-on-Insulator (SOI) field effect transistor (FET) operates in the enhancement mode without requiring inversion by setting the device's threshold voltage to twice the Fermi potential of the thin semiconductor layer in which the transistor is fabricated. The FET, referred to as a |
| 5105105 |
High speed logic and memory family using ring segment buffer |
April 14, 1992 |
| A logic and memory family using CMOS technology operates at high speeds using a Ring Segment Buffer to couple logic gates to one another in an integrated circuit chip, and to couple memory cells to other circuits to provide shift registers, triggers, clock pulse generators and other memo |
| 5030853 |
High speed logic and memory family using ring segment buffer |
July 9, 1991 |
| A logic and memory family using CMOS technology operates at high speeds using a Ring Segment Buffer to couple logic gates to one another in an integrated circuit chip, and to couple memory cells to other circuits to provide shift registers, triggers, clock pulse generators and other memo |
| 5001367 |
High speed complementary field effect transistor logic circuits |
March 19, 1991 |
| A high speed, high density, low power dissipation all parallel FET logic circuit includes a driving stage having a plurality of parallel FETs of a first conductivity type for receiving logic input signals and a load FET of second conductivity type connected to the common output of the dr |
| 4990974 |
Fermi threshold field effect transistor |
February 5, 1991 |
| A field effect transistor (FET) operates in the enhancement mode without requiring inversion by setting the device's threshold voltage to twice the Fermi potential of the semiconductor material. The FET, referred to as a Fermi Threshold FET or Fermi-FET, has a threshold voltage which is |
| 4984043 |
Fermi threshold field effect transistor |
January 8, 1991 |
| A field effect transistor (FET) operates in the enhancement mode without requiring inversion by setting the device's threshold voltage to twice the Fermi potential of the semiconductor material. The FET, referred to as a Fermi Threshold FET or Fermi-FET, has a threshold voltage which is |
