| Patent Number |
Title Of Patent |
Date Issued |
| D288922 |
Zero power random access memory package |
March 24, 1987 |
|
| 4722913 |
Doped semiconductor vias to contacts |
February 2, 1988 |
| In the manufacture of integrated circuits, an undoped wide band-gap semiconductor is used for the insulating layer to isolate the silicon substrate from the metal interconnection pattern. To provide conductive vias through the insulating layer for connection to the source and drain o |
| 4722060 |
Integrated-circuit leadframe adapted for a simultaneous bonding operation |
January 26, 1988 |
| A leadframe for an integrated circuit includes a set of individual leads temporarily connected in an array; each lead having an exterior portion shaped in a standard form and an interior portion shaped to form a standard array of contacts and to have the same spring constant for defl |
| 4716380 |
FET differential amplifier |
December 29, 1987 |
| A differential amplifier (10) has two input terminals (16,18), an output terminal (20) together with power terminals (12,14). The differential amplifier comprises two or more stages with each stage having a pull-up transistor (22) and a pull-down transistor (26). The first input terminal |
| 4714843 |
Semiconductor chip power supply monitor circuit arrangement |
December 22, 1987 |
| A circuit arrangement (13) for monitoring power supplies in N-channel CMOS devices, comprising elements for sampling of a bandgap voltage reference quantity (41), comparing the reference quantity to a monitored power supply voltage level (38), and compensating (49) for the offset voltage |
| 4714840 |
MOS transistor circuits having matched channel width and length dimensions |
December 22, 1987 |
| The voltage gain of an MOS transistor inverter stage is made independent of the device threshold voltages and of channel lengths by making the length and width of the channel region of the upper load transistor equal to the length and width of the channel region of the lower driver trans |
| 4685083 |
Improved nonvolatile memory circuit using a dual node floating gate memory cell |
August 4, 1987 |
| An improved nonvolatile memory has an adaptive system to regulate the charging current supplied to store data on nonvolatile storage nodes in order to provide acceptability low strain on the tunnel oxide and to compensate for process variations and change in the Fowler-Nordheim tunnel |
| 4655134 |
Method of branding a semiconductor chip package |
April 7, 1987 |
| A method for branding (labeling) a semiconductor chip package by warming the package prior to and subsequent to the branding resulting in a brand having greater clarity and permanency. A chip package is warmed to a temperature of about 95.degree. F. (35.degree. C.) to about 130.degree. F |
| 4653860 |
Programable mask or reticle with opaque portions on electrodes |
March 31, 1987 |
| A programable liquid crystal arrangement including parallel transparent plates and crossed, x-y addressable electrodes with a liquid crystal material disposed therebetween, in an optical system effective for fixing patterns or words of information in selected information storage media. |
| 4651305 |
Sense amplifier bit line isolation scheme |
March 17, 1987 |
| In a CMOS ROM memory arrangement, the use of the least significant column address bit to perform the dual function of even/odd bit line select and the disconnection of the selected bit line (17' and 17") from the sense amplifier (66) driven, in order to reduce its capacitive load, prior |
| 4651303 |
Non-volatile memory cell |
March 17, 1987 |
| A volatile/non-volatile integrated circuit memory cell combines a non-volatile cell (110) connected to a volatile cell (105) at a volatile node (118), in which data recall is effected through a DC-stable arrangement of transistor (142), (145) and (146) that does not employ a capacito |
| 4649471 |
Address-controlled automatic bus arbitration and address modification |
March 10, 1987 |
| A microcomputer includes I/O ports and registers which are mapped in memory space along with RAM and ROM and in which hardware invisible to the programmer performs a bus arbitration sequence to acquire an external bus when an off-chip reference requires the bus; and in which memory space |
| 4646306 |
High-speed parity check circuit |
February 24, 1987 |
| A high speed parity circuit uses a sequence of simplified exclusive-OR circuits responsive to data input terminals containing a data signal and its complement and terminating in a sense amplifier, together with an operating sequence in which the inputs to the sequence are grounded while |
| 4645952 |
High speed NOR gate |
February 24, 1987 |
| A high speed CMOS NOR gate employs a pair of cross-coupled inverters and a dual set of N-channel pulldown transistors (202, 203) at each of the nodes between the two inverters, together with small pullup transistor (205) on the output terminal that is permanently energized and a switchab |
| 4636988 |
CMOS memory arrangement with reduced data line compacitance |
January 13, 1987 |
| A CMOS memory arrangement having each of a plurality of data lines connected to a plurality of bitlines, at least one of said datalines having a lesser number of bitlines in order to decrease capacitance in slower signal paths and thereby increase the operating speed of the memory. A |
| 4634890 |
Clamping circuit finding particular application between a single sided output of a computer memo |
January 6, 1987 |
| A transistor arrangement for clamping the output node of a semiconductor memory, including an inverter to parallel with a transmission gate for producing a differential output signal. |
| 4627787 |
Chip selection in automatic assembly of integrated circuit |
December 9, 1986 |
| A method for removing selected integrated circuit dice from a wafer array of dice sequentially moves a striker above a tape to the underside of which the array is mounted and the knocks a die down from the array of dice into a receptacle for transport to further processing stages. |
| 4627151 |
Automatic assembly of integrated circuits |
December 9, 1986 |
| A system for the assembly and packaging of integrated circuits employs circuit dice that have contact pads in a standard array; a leadframe having leads configured to have the same spring constant; a method for removing selected dice from a wafer array under computer control; and a m |
| 4627031 |
CMOS memory arrangement |
December 2, 1986 |
| CMOS memory arrangement including a circuit for setting the dataline voltage at a predetermined bias level, the circuit comprising four MOS transistors, the first, second and third and the first and fourth thereof being connected in respective series from VCC to ground, the gates of the |
| 4626985 |
Single-chip microcomputer with internal time-multiplexed address/data/interrupt bus |
December 2, 1986 |
| A microcomputer architecture permits communication between a CPU and same-chip ports and input/output circuits to be carried only over a multiplexed address/data/interrupt bus, thereby permitting modified I/O hardware or other circuits to be included in the microcomputer without dist |
| 4626713 |
Trip-point clamping circuit for a semiconductor device |
December 2, 1986 |
| A trip point clamping circuit for maintaining the voltage level at a node of connection to a sense arrangement including an inverter within defined bounds at the trip point of the inverter, the clamping circuit including a reference voltage, a source of similar current levels, a switch f |
| 4626167 |
Manipulation and handling of integrated circuit dice |
December 2, 1986 |
| A method for inverting and handling integrated circuit dice employs rotating apparatus for rotating a chip carrier by 180 degrees to invert and transfer dice from one set of receptacles to another; together with an apparatus for precisely aligning dice resting at random positions within |
| 4622479 |
Bootstrapped driver circuit for high speed applications |
November 11, 1986 |
| An improved integrated circuit driver circuit switches a relatively large load at high speed by means of a bootstrapping capacitor that bootstraps an output transistor a fixed time after the transistor has started to drive the load. |
| 4621208 |
CMOS output buffer |
November 4, 1986 |
| A synchronizing buffer arrangement for a CMOS memory with output drive transistors receiving one of a pair of input data signals, and being subject to the pull-up and pull-down support of the other of said data signals. |
| 4618786 |
Precharge circuit for enhancement mode memory circuits |
October 21, 1986 |
| A circuit for precharging the gates of pass transistor that will be subsequently bootstrapped employs a precharge circuit that generates a precharge pulse having magnitude greater than Vcc and distributes the pulse to a number of gate control circuits that raise the pass transistor g |
| 4618785 |
CMOS sense amplifier with level shifter |
October 21, 1986 |
| A common mode gain enhancing CMOS differential sense amplifier for a static RAM memory, straddled by level shifting circuits during the respective differential inputs to the sense amplifier. |
| 4610000 |
ROM/RAM/ROM patch memory circuit |
September 2, 1986 |
| An integrated circuit contains ROM, ROM patch and RAM memories on a common substrate with a standard pinout. The ROM and RAM fill the address space allowed by the address pins. Control of the patch memory without the use of special control pins is accomplished by writing to a ROM address |
| 4609985 |
Microcomputer with severable ROM |
September 2, 1986 |
| A microcomputer has provision for both on-chip ROM (on the same chip as the CPU) and off-chip ROM and which may operate with only on-chip ROM as only off-chip ROM has the hardware capability to disable on-chip ROM permanently, so that chips having defective ROM may be salvaged by being |
| 4609833 |
Simple NMOS voltage reference circuit |
September 2, 1986 |
| A simple, compact voltage reference circuit for an NMOS integrated circuit comprises a series connected depletion transistor with its gate at ground and an enhancement transistor with its gate connected to an output node between the two transistors. |
| 4604732 |
Power supply dependent voltage reference circuit |
August 5, 1986 |
| A circuit adapted for use in comparing voltages in a manner that is insensitive to power supply variations includes a pair of reference cells controlling the reference voltage of a sense amplifier through control of a pair of reference transistors and an input circuit for conditioning da |
| 4597714 |
Robot gripper for integrated circuit leadframes |
July 1, 1986 |
| An apparatus for gripping a thin flexible object located within a gripping plane having a transverse axis and a longitudinal axis perpendicular to each other and to a linear axis which is perpendicular to the gripping plane, includes first and second sets of gripper claws for gripping th |
| 4595498 |
Water-polishing loop |
June 17, 1986 |
| A water purification system includes an ion-exchange unit for producing high-resistivity water, followed by ozone exposure and ultraviolet sterilizer units that oxidize organics and also reduce resistivity, followed by a vacuum degassification unit to restore high resistivity. |
| 4593214 |
Circuit for discharging bootstrapped nodes in integrated circuits with the use of transistors de |
June 3, 1986 |
| A sub-circuit for discharging a relatively high voltage node in an integrated circuit includes an enhancement transistor connected between ground and an intermediate node and a depletion transistor connected between the intermediate node and the high voltage node, both of the transis |
| 4592481 |
Resilient stopper for integrated circuit magazine |
June 3, 1986 |
| A resilient stopper (40) for retaining IC's (12) in magazine (10) having a rectangular section (16) of height (h) and width (w) is disclosed. The stopper has a tubular body portion (42) of thickness (t), inner diameter (d) and width substantially (w); and a tab (50) within the stopper of |
| 4590504 |
Nonvolatile MOS memory cell with tunneling element |
May 20, 1986 |
| A nonvolatile memory cell (16) is fabricated on a substrate (12) and includes a source region (46) and drain regions (48, 50 and 52). Step oxides (40, 42 and 44) are fabricated respectively over the regions (46, 48 and 52). A gate oxide (58) is formed between the step oxides (40 and |
| 4586170 |
Semiconductor memory redundant element identification circuit |
April 29, 1986 |
| A test circuit (10) for a semiconductor memory is provided. The semiconductor memory includes a redundant decoder (70) for receiving memory address signals (66, 68) which is connected to a redundant circuit element via a signal line (72). The redundant decoder (70) can be programmed |
