| Patent Number |
Title Of Patent |
Date Issued |
| RE40138 |
Method for improving hot carrier lifetime via a nitrogen implantation procedure performed before |
March 4, 2008 |
| A process for fabricating input/output, N channel, (I/O NMOS) devices, featuring an ion implanted nitrogen region, used to reduce hot carrier electron, (HEC), injection, has been developed. The process features implanting a nitorgen region, at the interface of an overlying silicon ox |
| RE40007 |
In-situ strip process for polysilicon etching in deep sub-micron technology |
January 22, 2008 |
| A new method of patterning the polysilicon layer in the manufacture of an integrated circuit device has been achieved. A polysilicon layer is provided overlying a semiconductor substrate. The polysilicon layer may overlie a gate oxide layer and thereby comprise the polysilicon gate for |
| RE39913 |
Method to control gate CD |
November 6, 2007 |
| The invention is a process for reducing variations in CD from wafer to wafer. It begins by increasing all line widths in the original pattern data file by a fixed amount that is sufficient to ensure that all lines will be wider than the lowest acceptable CD value. Using a reticle gen |
| RE39273 |
Hard masking method for forming patterned oxygen containing plasma etchable layer |
September 12, 2006 |
| A method for forming a patterned microelectronics layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an oxygen containing plasma etchable microelectronics layer. Ther |
| RE38914 |
Dual damascene patterned conductor layer formation method without etch stop layer |
December 6, 2005 |
| A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate having a contact region formed therein. There is then formed upon the substrate and covering the contact region a blanket first dielectric layer formed of a |
| 7629690 |
Dual damascene process without an etch stop layer |
December 8, 2009 |
| A non-ESL semiconductor interconnection structure and a method of forming the same are provided. The non-ESL semiconductor interconnection structure includes a first low-k dielectric layer comprising a first region and a second region overlying the substrate, a plurality of conductiv |
| 7629655 |
Semiconductor device with multiple silicide regions |
December 8, 2009 |
| A system and method for forming a semiconductor device with a reduced source/drain extension parasitic resistance is provided. An embodiment comprises implanting two metals (such as ytterbium and nickel for an NMOS transistor or platinum and nickel for a PMOS transistor) into the sou |
| 7629275 |
Multiple-time flash anneal process |
December 8, 2009 |
| A method of forming an integrated circuit is provided. The method includes performing a multiple-time flash anneal process to a wafer, wherein the multiple-time flash anneal process comprises preheating the wafer to a first preheat temperature; performing a first flash on the wafer with |
| 7629273 |
Method for modulating stresses of a contact etch stop layer |
December 8, 2009 |
| A method for forming a semiconductor structure includes providing a substrate comprising a first device region, forming a metal-oxide-semiconductor (MOS) device in the first device region, forming a stressed layer over the MOS device, and performing a post-treatment to modulate a str |
| 7625801 |
Silicide formation with a pre-amorphous implant |
December 1, 2009 |
| A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, forming a silicon-containing compound stressor adjacent the gate stack, implanting non-siliciding ions into the silicon-containing compoun |
| 7615841 |
Design structure for coupling noise prevention |
November 10, 2009 |
| A semiconductor structure for preventing coupling noise in integrated circuits and a method of forming the same are provided. The semiconductor structure includes a signal-grounded seal ring. The seal ring includes a plurality of metal lines, each in a respective metal layer and surr |
| 7615426 |
PMOS transistor with discontinuous CESL and method of fabrication |
November 10, 2009 |
| A transistor having a discontinuous contact etch stop layer comprising: a substrate having a surface, a gate dielectric on said surface of said substrate, a gate electrode on said gate dielectric, a spacer along a sidewall of said gate dielectric and gate electrode, a source and a drain |
| 7613535 |
Independent, self-contained, risk isolated, sectional CIM design for extremely large scale facto |
November 3, 2009 |
| A semiconductor manufacturing system includes a centralized computer integrated manufacturing (CIM) system; a plurality of sectional CIM systems respectively associated with a plurality of manufacturing facilities and coupled with the centralized CIM system; and a centralized basic r |
| 7613057 |
Circuit and method for a sense amplifier |
November 3, 2009 |
| A circuit and method for providing a sense amplifier for a DRAM memory with reduced distortion in a control signal, the sense amplifier particularly useful for embedding DRAM memory with other logic and memory functions in an integrated circuit. A sense enable circuit is provided for |
| 7612984 |
Layout for capacitor pair with high capacitance matching |
November 3, 2009 |
| An integrated circuit device includes a capacitor array, which includes unit capacitors arranged in rows and columns, wherein each unit capacitor is formed of two electrically insulated capacitor plates. The unit capacitors include at least one first unit capacitor in each row and in |
| 7612605 |
Bootstrap voltage generating circuits |
November 3, 2009 |
| A bootstrap voltage generating circuit includes a bias circuit having a first end coupled to a first power source node having an operation voltage, and a second end coupled to a low voltage reference potential, wherein a voltage at the first end is related to the operation voltage in |
| 7612451 |
Reducing resistivity in interconnect structures by forming an inter-layer |
November 3, 2009 |
| An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, and a damascene structure in the opening. The damascene structure includes a m |
| 7612405 |
Fabrication of FinFETs with multiple fin heights |
November 3, 2009 |
| A semiconductor structure includes a first semiconductor strip extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the first semiconductor strip has a first height. A first insulating region is formed in the semiconductor substrate and |
| 7612389 |
Embedded SiGe stressor with tensile strain for NMOS current enhancement |
November 3, 2009 |
| MOS devices having localized stressors are provided. Embodiments of the invention comprise a gate electrode formed over a substrate and source/drain regions formed on either side of the gate electrode. The source/drain regions include an embedded stressor and a capping layer on the e |
| 7612364 |
MOS devices with source/drain regions having stressed regions and non-stressed regions |
November 3, 2009 |
| A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the stressor comprises an impurity of a first conductivity type; and a |
| 7611963 |
Method for forming a multi-layer shallow trench isolation structure in a semiconductor device |
November 3, 2009 |
| A method for forming a multi-layer shallow trench isolation structure in a semiconductor device is described. In one embodiment, the method includes etching a shallow trench in a silicon substrate of a semiconductor device and forming a dielectric liner layer on a floor and walls of the |
| 7611960 |
Method and system for wafer backside alignment |
November 3, 2009 |
| Disclosed is a method and a system for wafer backside alignment. A zero mark patterning on front side of a substrate. A plurality of layers are deposited on the front side of the substrate. The wafer is flipped over with backside of the substrate facing up, and a through wafer etching is |
| 7611938 |
Semiconductor device having high drive current and method of manufacture therefor |
November 3, 2009 |
| A method comprises forming a first semiconductor device in a substrate, where the first semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a first thickness, and raised source and drain regions disposed on either side |
| 7611937 |
High performance transistors with hybrid crystal orientations |
November 3, 2009 |
| A method of forming a semiconductor structure having a hybrid crystal orientation and forming MOSFETs having improved performance on the semiconductor structure is provided. The method includes providing a substrate comprising a buried oxide (BOX) on a first semiconductor layer, and |
| 7611825 |
Photolithography method to prevent photoresist pattern collapse |
November 3, 2009 |
| A method comprises forming a BARC layer on a substrate, treating the BARC layer to make its surface hydrophilic, forming a photoresist layer on the treated BARC layer, exposing the photoresist layer to a predetermined pattern, and developing the photoresist layer to form patterned ph |
| 7608926 |
Nonvolatile semiconductor memory device |
October 27, 2009 |
| A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the cond |
| 7608515 |
Diffusion layer for stressed semiconductor devices |
October 27, 2009 |
| A diffusion layer for semiconductor devices is provided. In accordance with embodiments of the present invention, a semiconductor device, such as a transistor, comprises doped regions surrounded by a diffusion barrier. The diffusion barrier may be formed by recessing regions of the s |
| 7605407 |
Composite stressors with variable element atomic concentrations in MOS devices |
October 20, 2009 |
| A semiconductor device includes a semiconductor substrate, a gate stack on the semiconductor substrate, and a stressor adjacent the gate stack and having at least a portion in the semiconductor substrate, wherein the stressor comprises an element for adjusting a lattice constant of the |
| 7602471 |
Apparatus and method for particle monitoring in immersion lithography |
October 13, 2009 |
| The present disclosure provides an immersion lithography system. The system includes an imaging lens having a front surface; a substrate stage positioned underlying the front surface of the imaging lens; an immersion fluid retaining structure having a fluid inlet and a fluid outlet, |
| 7601466 |
System and method for photolithography in semiconductor manufacturing |
October 13, 2009 |
| A method for photolithography in semiconductor manufacturing includes providing a mask with first and second focus planes for a wafer. The wafer includes corresponding first and second wafer regions. The first wafer region receives a first image during a first exposure utilizing the |
| 7599215 |
Magnetoresistive random access memory device with small-angle toggle write lines |
October 6, 2009 |
| Disclosed herein are toggle-mode magnetoresistive random access memory (MRAM) devices having small-angle toggle write lines, and related methods of toggle-mode switching MRAM devices. Also disclosed are layouts for MRAM devices constructed according to the disclosed principles. Generally |
| 7598523 |
Test structures for stacking dies having through-silicon vias |
October 6, 2009 |
| A semiconductor die including a test structure is provided. The semiconductor die includes a loop-back formed on a surface of the semiconductor die. The loop-back structure includes a first bonding pad on a first surface; and a second bonding pad on the first surface, wherein the fir |
| 7598130 |
Method for reducing layout-dependent variations in semiconductor devices |
October 6, 2009 |
| A method for forming an integrated circuit includes providing a semiconductor substrate, forming a re-implantation blocking layer over the semiconductor substrate, forming a mask over the re-implantation blocking layer, patterning the mask to form an opening, wherein a portion of the |
| 7592858 |
Circuit and method for a gate control circuit with reduced voltage stress |
September 22, 2009 |
| Circuit and method for a gate control output circuit having reduced voltage stress on the devices is disclosed. In a circuit of MOS transistors for supplying an output to control a transfer gate, the output having a high voltage level that exceeds a supply voltage, first and second c |
| 7592710 |
Bond pad structure for wire bonding |
September 22, 2009 |
| A bond pad structure of an integrated circuit is provided. The bond pad structure includes a conductive bond pad, a first dielectric layer underlying the bond pad, and an M.sub.top plate located in the first dielectric layer and underlying the bond pad. The M.sub.top plate is a solid |
| 7590017 |
DRAM bitline precharge scheme |
September 15, 2009 |
| Circuits and method for precharging a pair of complementary bitlines in a dynamic random access memory (DRAM). Both bitlines are precharged to VDD during a precharge phase, and during a sensing phase, the voltage of one of the pair of complementary bitlines is adjusted from VDD to a refe |
| 7589387 |
SONOS type two-bit FinFET flash memory cell |
September 15, 2009 |
| A 2-bit FinFET flash memory cell capable of storing 2 bits and a method of forming the same are provided. The memory cell includes a semiconductor fin on a top surface of a substrate, a gate insulation film on the top surface and sidewalls of a channel section of the semiconductor fin, a |
| 7588995 |
Method to create damage-free porous low-k dielectric films and structures resulting therefrom |
September 15, 2009 |
| Low dielectric constant dielectric films having a high degree of porosity suffer from poor mechanical strength and can be damaged during processing steps. Damage can be substantially eliminated or minimized by stuffing the pores of the dielectric film with a material that substantially f |
| 7588993 |
Alignment for backside illumination sensor |
September 15, 2009 |
| An apparatus and manufacturing method thereof, wherein an integrated circuit is located in a first region of a substrate having first and second opposing major surfaces, and wherein an alignment mark is located in a second region of the substrate and extends through the substrate bet |
| 7588963 |
Method of forming overhang support for a stacked semiconductor device |
September 15, 2009 |
| A stacked, multi-die semiconductor device and method of forming thereof. A preferred embodiment comprises disposing a stack of semiconductor dies to a substrate. The stacking arrangement is such that a lateral periphery of an upper die is cantilevered over a lower die thereby forming a r |
| 7588946 |
Controlling system for gate formation of semiconductor devices |
September 15, 2009 |
| A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step height |
| 7586176 |
Semiconductor device with crack prevention ring |
September 8, 2009 |
| A crack prevention ring at the exterior edge of an integrated circuit prevents delamination and cracking during the separation of the integrated circuits into individual die. The crack prevention ring extends vertically into a semiconductor workpiece to at least a metallization layer |
| 7585737 |
Method of manufacturing double diffused drains in semiconductor devices |
September 8, 2009 |
| A method of manufacturing double diffused drains in a semiconductor device. An embodiment comprises forming a gate dielectric layer on a substrate, and masking and patterning the gate dielectric layer. Once the gate dielectric layer has been patterned, a second dielectric layer, havi |
| 7583484 |
Circuit and method for ESD protection |
September 1, 2009 |
| A sensor for electrostatic discharge (ESD) protection includes a voltage divider and a device coupled thereto. The sensor is coupled to an input terminal of the sensor, wherein a voltage drop occurs across the voltage divider and a high state voltage is generated at an output terminal of |
| 7582947 |
High performance device design |
September 1, 2009 |
| A semiconductor structure having a recessed active region and a method for forming the same are provided. The semiconductor structure comprises a first and a second isolation structure having an active region therebetween. The first and second isolation structures have sidewalls with |
| 7582538 |
Method of overlay measurement for alignment of patterns in semiconductor manufacturing |
September 1, 2009 |
| A method for semiconductor manufacturing includes forming an overlay target having a pattern formed by a first mask layer and an adjacent layer. The overlay target is exposed to radiation. As a result, reflective beams can be detected from the pattern and the adjacent layer and the l |
| 7579859 |
Method for determining time dependent dielectric breakdown |
August 25, 2009 |
| The current invention provides a method of determining the lifetime of a semiconductor device due to time dependent dielectric breakdown (TDDB). This method includes providing a plurality of samples of dielectric layer disposed as a gate dielectric layer of a MOS transistor, approximatin |
| 7579646 |
Flash memory with deep quantum well and high-K dielectric |
August 25, 2009 |
| A flash memory cell includes a substrate and a gate structure formed on the substrate. The gate structure includes a tunneling layer over the substrate, a storage layer over the tunneling layer, a blocking layer over the storage layer, and a gate electrode over the dielectric. The st |
| 7579612 |
Resistive memory device having enhanced resist ratio and method of manufacturing same |
August 25, 2009 |
| Disclosed herein are new resistive memory devices having one or more buffers layer surrounding a dielectric layer. By inserting one or more buffer layers around the dielectric layer of the device, the resistive ratio of the device is highly enhanced. For example, tests using this uni |
| 7579248 |
Resolving pattern-loading issues of SiGe stressor |
August 25, 2009 |
| A method for improving uniformity of stressors of MOS devices is provided. The method includes forming a gate dielectric over a semiconductor substrate, forming a gate electrode on the gate dielectric, forming a spacer on respective sidewalls of the gate electrode and the gate dielec |
