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Taiwan Semiconductor Manufacturing Company, Ltd. Patents
Taiwan Semiconductor Manufacturing Company, Ltd.
Hsin-Chu, TW
No. of patents:

Patent Number Title Of Patent Date Issued
RE43673 Dual gate dielectric scheme: SiON for high performance devices and high K for low power devices September 18, 2012
A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially de
RE42556 Apparatus for method for immersion lithography July 19, 2011
An apparatus for immersion lithography that includes an imaging lens which has a front surface, a .Iadd.fluid-containing wafer stage for supporting a .Iaddend.wafer that has a top surface to be exposed positioned spaced-apart and juxtaposed to the front surface of the imaging lens, .
RE42457 Methods of packaging an integrated circuit and methods of forming an integrated circuit package June 14, 2011
The present invention includes an integrated circuit package, a ball-grid array integrated circuit package, a method of packaging an integrated circuit, and a method of forming an integrated circuit package. According to one aspect, the present invention provides an integrated circuit
RE42332 Integrated circuit package, ball-grid array integrated circuit package May 10, 2011
The present invention includes an integrated circuit package, a ball-grid array integrated circuit package, a method of packaging an integrated circuit, and a method of forming an integrated circuit package. According to one aspect, the present invention provides an integrated circuit
RE41935 Method for preventing low-k dielectric layer cracking in multi-layered dual damascene metallizat November 16, 2010
A method for plasma treatment of anisotropically etched openings to improve a crack initiation and propagation resistance including providing a semiconductor wafer having a process surface including anisotropically etched openings extending at least partially through a dielectric ins
RE40138 Method for improving hot carrier lifetime via a nitrogen implantation procedure performed before March 4, 2008
A process for fabricating input/output, N channel, (I/O NMOS) devices, featuring an ion implanted nitrogen region, used to reduce hot carrier electron, (HEC), injection, has been developed. The process features implanting a nitorgen region, at the interface of an overlying silicon ox
RE40007 In-situ strip process for polysilicon etching in deep sub-micron technology January 22, 2008
A new method of patterning the polysilicon layer in the manufacture of an integrated circuit device has been achieved. A polysilicon layer is provided overlying a semiconductor substrate. The polysilicon layer may overlie a gate oxide layer and thereby comprise the polysilicon gate for
RE39913 Method to control gate CD November 6, 2007
The invention is a process for reducing variations in CD from wafer to wafer. It begins by increasing all line widths in the original pattern data file by a fixed amount that is sufficient to ensure that all lines will be wider than the lowest acceptable CD value. Using a reticle gen
RE39273 Hard masking method for forming patterned oxygen containing plasma etchable layer September 12, 2006
A method for forming a patterned microelectronics layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an oxygen containing plasma etchable microelectronics layer. Ther
RE38914 Dual damascene patterned conductor layer formation method without etch stop layer December 6, 2005
A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate having a contact region formed therein. There is then formed upon the substrate and covering the contact region a blanket first dielectric layer formed of a
8589847 Circuits and methods for programmable transistor array November 19, 2013
A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and
8589830 Method and apparatus for enhanced optical proximity correction November 19, 2013
Provided is an integrated circuit (IC) design method. The method includes receiving an IC design layout having a feature with an outer boundary, performing a dissection on the feature to divide the outer boundary into a plurality of segments, and performing, using the segments, an optica
8589828 Reduce mask overlay error by removing film deposited on blank of mask November 19, 2013
A method for reducing layer overlay errors by synchronizing the density of mask material in the frame area across the masks in a set is disclosed. An exemplary method includes creating a mask design database corresponding to a mask and containing a die area with one or more dies and
8587992 Data-aware SRAM systems and methods forming same November 19, 2013
Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage sig
8587368 Bandgap reference circuit with an output insensitive to offset voltage November 19, 2013
A method includes generating a first current, wherein the first current flows through a first resistor and a first bipolar transistor. A first end of the first resistor is serially connected to an emitter-collector path of the first bipolar transistor, and a second end of the resistor is
8587089 Seal ring structure with polyimide layer adhesion November 19, 2013
The present disclosure provides a semiconductor device, including a substrate having a seal ring region and a circuit region, a seal ring structure disposed over the seal ring region, a first passivation layer disposed over the seal ring structure, the first passivation layer having
8587084 Seamless multi-poly structure and methods of making same November 19, 2013
A sensor array is integrated onto the same chip as core logic. The sensor array uses a first polysilicon and the core logic uses a second polysilicon. The first polysilicon is etched to provide a tapered profile edge in the interface between the sensor array and the core logic regions
8587075 Tunnel field-effect transistor with metal source November 19, 2013
A semiconductor device includes a channel region; a gate dielectric over the channel region; and a gate electrode over the gate dielectric. A first source/drain region is adjacent the gate dielectric, wherein the first source/drain region is a semiconductor region and of a first cond
8587073 High voltage resistor November 19, 2013
Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically c
8586469 Metal layer end-cut flow November 19, 2013
A method of patterning a metal layer is disclosed. The method includes providing a substrate and forming a material layer over the substrate. The method includes forming a second material layer over the first material layer. The method includes performing a first patterning process t
8586452 Methods for forming semiconductor device structures November 19, 2013
The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
8586436 Method of forming a variety of replacement gate types including replacement gate types on a hybr November 19, 2013
Provided is a method and device that includes providing for a plurality of differently configured gate structures on a substrate. For example, a first gate structure associated with a transistor of a first type and including a first dielectric layer and a first metal layer; a second gate
8586408 Contact and method of formation November 19, 2013
A system and method for forming contacts is provided. An embodiment comprises forming the contacts on a substrate and then coining the contacts by physically shaping them using, e.g., a molding chamber. The physical shaping of the contacts may be performed using a patterned portion o
8586290 Patterning process and chemical amplified photoresist composition November 19, 2013
A lithography method includes forming a photosensitive layer on a substrate, exposing the photosensitive layer, baking the photosensitive layer, and developing the exposed photosensitive layer. The photosensitive layer includes a polymer that turns soluble to a base solution in respo
8584052 Cell layout for multiple patterning technology November 12, 2013
A system and method for providing a cell layout for multiple patterning technology is provided. An area to be patterned is divided into alternating sites corresponding to the various masks. During a layout process, sites located along a boundary of a cell are limited to having patter
8582352 Methods and apparatus for FinFET SRAM cells November 12, 2013
Methods and apparatus for providing finFET SRAM cells. An SRAM cell structure is provided including a central N-well region and a first and a second P-well region on opposing sides of the central N-well region, having an area ratio of the N-well region to the P-well regions between 8
8581423 Double solid metal pad with reduced area November 12, 2013
An integrated circuit structure includes a bond pad; an Mtop pad located directly underlying the bond pad; an Mtop-1 pad having at least a portion directly underlying the Mtop pad, wherein at least one of the Mtop pad and the Mtop-1 pad has a horizontal dimension smaller than a horizonta
8581418 Multi-die stacking using bumps with different sizes November 12, 2013
A device includes a first die having a first side and a second side opposite to first side, the first side includes a first region and a second region, and a first metal bump of a first horizontal size formed on the first region of the first side of the first die. A second die is bon
8581402 Molded chip interposer structure and methods November 12, 2013
Apparatus and methods for providing a molded chip interposer structure and assembly. A molded chip structure having at least two integrated circuit dies disposed within a mold compound is provided having the die bond pads on the bottom surface; and solder bumps are formed in the open
8581389 Uniformity control for IC passivation structure November 12, 2013
The present disclosure involves a semiconductor device. The semiconductor device includes a wafer containing an interconnect structure. The interconnect structure includes a plurality of vias and interconnect lines. The semiconductor device includes a first conductive pad disposed ov
8581347 Forming bipolar transistor through fast EPI-growth on polysilicon November 12, 2013
Provided is a semiconductor device that includes a first transistor and a second transistor that are formed on the same substrate. The first transistor includes a first collector, a first base, and a first emitter. The first collector includes a first doped well disposed in the subst
8581250 Method and apparatus of fabricating a pad structure for a semiconductor device November 12, 2013
The present disclosure involves a semiconductor device. The semiconductor device includes a substrate and an interconnect structure that is formed over the substrate. The interconnect structure has a plurality of metal layers. A first region and a second region each extend through both t
8581204 Apparatus for monitoring ion implantation November 12, 2013
An apparatus for monitoring an ion distribution of a wafer comprises a first sensor and a sensor. The first sensor, the second sensor and the wafer are placed in an effective range of a uniform ion implantation current profile. A controller determines the ion dose of each region of t
8580683 Apparatus and methods for molding die on wafer interposers November 12, 2013
Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spac
8580682 Cost-effective TSV formation November 12, 2013
A device includes a substrate having a first surface, and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the substrate. A dielectric layer is disposed over the substrate. A metal pad is disposed in th
8580657 Protecting sidewalls of semiconductor chips using insulation films November 12, 2013
A method of forming an integrated circuit structure includes providing a wafer having a first semiconductor chip, a second semiconductor chip, and a scribe line between and adjoining the first semiconductor chip and the second semiconductor chip; forming a notch in the scribe line, where
8580647 Inductors with through VIAS November 12, 2013
A device using an inductor with one or more through vias, and a method of manufacture is provided. In an embodiment, an inductor is formed in one or more of the metallization layers. One or more through vias are positioned directly below the inductor. The through vias may extend thro
8580641 Techniques providing high-k dielectric metal gate CMOS November 12, 2013
A method for manufacturing a semiconductor device includes forming a first dummy gate on a substrate, performing a doping process to the substrate, thereby forming a source and a drain at sides of the first dummy gate, performing a first high temperature annealing to activate the sou
8580614 Embedded wafer-level bonding approaches November 12, 2013
A method includes providing a carrier with an adhesive layer disposed thereon; and providing a die including a first surface, a second surface opposite the first surface. The die further includes a plurality of bond pads adjacent the second surface; and a dielectric layer over the pl
8580594 Method of fabricating a semiconductor device having recessed bonding site November 12, 2013
The present disclosure provides a method including providing a first substrate; and forming a microelectromechanical system (MEMS) device on a first surface of the first substrate. A bond pad is formed on at least one bonding site on the first surface of the first substrate. The bonding
8577717 Method and system for predicting shrinkable yield for business assessment of integrated circuit November 5, 2013
A method and a system for predicting shrinkable yield for business assessment of integrated circuit design shrink are provided. An assessment system is provided to determine cost benefits of a design shrink of an integrated circuit chip. A cost benefit analysis across different desig
8575965 Internal clock gating apparatus November 5, 2013
An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino logic block is configured to receive the clock signal and a control signal from an output o
8575727 Gate structures November 5, 2013
A semiconductor device is provided. The device includes a semiconductor substrate, first and second projections extending upwardly from the substrate, the projections having respective first and second channel regions therein, and a first gate structure engaging the first projection
8575717 Integrated circuit device and method of manufacturing the same November 5, 2013
Provided is a integrated circuit device and a method for fabricating the same. The integrated circuit device includes a semiconductor substrate having a dielectric layer disposed over the semiconductor substrate and a passive element disposed over the dielectric layer. The integrated
8574995 Source/drain doping method in 3D devices November 5, 2013
The present disclosure provides methods of semiconductor device fabrication for 3D devices. One method includes provide a substrate having a recess and forming a doping layer on the substrate and in the recess. The substrate is then annealed. The annealing drives dopants of a first t
8572537 Accurate parasitic capacitance extraction for ultra large scale integrated circuits October 29, 2013
A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via sha
8572520 Optical proximity correction for mask repair October 29, 2013
Integrated circuit (IC) methods for optical proximity correction (OPC) modeling and mask repair are described. The methods include use of an optical model that generates a simulated aerial image from an actual aerial image obtained in an optical microscope system. In the OPC modeling
8572519 Method and apparatus for reducing implant topography reflection effect October 29, 2013
Embodiments of the present disclosure provide methods and apparatuses for integrated circuits. An exemplary integrated circuit (IC) method includes providing an IC design layout that includes a design feature; determining a dimensional difference between the design feature and a correspo
8570698 ESD protection for FinFETs October 29, 2013
An embodiment is a semiconductor device comprising a receiver circuit comprising fin field effect transistors (FinFETs), a transceiver circuit comprising FinFETs, and a transmit bus electrically coupling the receiver circuit and the transceiver circuit, wherein the receiver circuit and t
8569886 Methods and apparatus of under bump metallization in packaging semiconductor devices October 29, 2013
Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation

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