| Patent Number |
Title Of Patent |
Date Issued |
| 7615837 |
Lithography device for semiconductor circuit pattern generation |
November 10, 2009 |
| General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membr |
| 7604306 |
Reticle box transport cart |
October 20, 2009 |
| A new transportation cart is provided that separates each reticle box or container from other reticle boxes contained in the cart. The transportation cart provides additional shock absorption, thus eliminating effects of vibration of the reticles, the transportation cart is equipped |
| 7582934 |
Isolation spacer for thin SOI devices |
September 1, 2009 |
| A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa. |
| 7580129 |
Method and system for improving accuracy of critical dimension metrology |
August 25, 2009 |
| A method for improving accuracy of optical critical dimension measurement of a substrate is provided. A process parameter that influences the refractive index and extinction coefficient of a thin film in the substrate is identified. A refractive index and extinction coefficient acros |
| 7576374 |
Semiconductor device with robust polysilicon fuse |
August 18, 2009 |
| A new method is provided to create a polysilicon fuse. The invention provides for applying a first oxide plasma treatment to the surface of the created polysilicon fuse, creating a thin layer of native oxide over the surface of the created polysilicon fuse, followed by a DI water rin |
| 7573736 |
Spin torque transfer MRAM device |
August 11, 2009 |
| The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a |
| 7571421 |
System, method, and computer-readable medium for performing data preparation for a mask design |
August 4, 2009 |
| A method, computer-readable medium, and system for performing data preparation are provided. An integrated circuit design is received, and a plurality of pre-optical proximity correction processes are invoked such that the plurality of pre-optical proximity correction processes are p |
| 7571021 |
Method and system for improving critical dimension uniformity |
August 4, 2009 |
| A method for improving critical dimension of a substrate is provided. Manufacturing data of a plurality of critical dimension deviations corresponding to a plurality of areas on the substrate is collected. A plurality of sensitivity data corresponding to the plurality of areas is als |
| 7564556 |
Method and apparatus for lens contamination control |
July 21, 2009 |
| The present disclosure provides a method for measuring lens contamination in a lithography apparatus. The method includes imaging an asymmetric pattern utilizing a lens system and measuring an alignment offset of the asymmetric pattern associated with the lens system. A contamination of |
| 7563653 |
ESD protection for high voltage applications |
July 21, 2009 |
| An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of |
| 7547605 |
Microelectronic device and a method for its manufacture |
June 16, 2009 |
| Provided are a microelectronic device and a method for its manufacture. In one example, the method includes providing a semiconductor substrate layer having a first material (e.g., silicon or silicon germanium). An insulating layer is formed on the semiconductor substrate layer with |
| 7545001 |
Semiconductor device having high drive current and method of manufacture therefor |
June 9, 2009 |
| A semiconductor device including an isolation region located in a substrate, an NMOS device located partially over a surface of the substrate, and a PMOS device isolated from the NMOS device by the isolation region and located partially over the surface. A first one of the NMOS and P |
| 7538025 |
Dual damascene process flow for porous low-k materials |
May 26, 2009 |
| A method of forming a dual damascene opening comprising the following steps. A structure having an overlying exposed conductive layer formed thereover is provided. A dielectric layer is formed over the exposed conductive layer. An anti-reflective coating layer is formed over the diel |
| 7534725 |
Advanced process control for semiconductor processing |
May 19, 2009 |
| An advanced process control (APC) method for semiconductor fabrication is provided. A first substrate and a second substrate are provided. The first substrate and the second substrate include a dielectric layer. A first etch process parameter for the first substrate is determined. A |
| 7531399 |
Semiconductor devices and methods with bilayer dielectrics |
May 12, 2009 |
| A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that includes: providing a |
| 7514730 |
Method of fabricating a non-floating body device with enhanced performance |
April 7, 2009 |
| Provided is a semiconductor transistor device including a substrate having at least two regions, a semiconductive region extending to a first surface of the substrate and an insulative region extending to a second surface of the substrate. The semiconductor transistor device also inc |
| 7514348 |
Sidewall coverage for copper damascene filling |
April 7, 2009 |
| A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in |
| 7505206 |
Microlens structure for improved CMOS image sensor sensitivity |
March 17, 2009 |
| A method of manufacturing a microlens device by depositing a microlens material layer over a substrate that includes photo-sensors. The microlens material layer is then exposed and developed to define microlens material elements, including first microlens material elements and second |
| 7501227 |
System and method for photolithography in semiconductor manufacturing |
March 10, 2009 |
| A method for producing a pattern on a substrate includes providing at least one exposure of the pattern onto a layer of the substrate by a higher-precision lithography mechanism and providing at least one exposure of the pattern onto a layer of the substrate by a lower-precision lith |
| 7494830 |
Method and device for wafer backside alignment overlay accuracy |
February 24, 2009 |
| A method for wafer backside alignment overlay accuracy includes forming a buried layer on a front-side of a wafer; forming a conductive layer on the buried layer and patterning a first test structure and a second test structure therein; forming an etch stop layer on the conductive layer; |
| 7432192 |
Post ECP multi-step anneal/H.sub.2 treatment to reduce film impurity |
October 7, 2008 |
| A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process a |
| 7407835 |
Localized slots for stress relieve in copper |
August 5, 2008 |
| In accordance with the objectives of the invention a new method is provided for the creation of interconnect metal. Current industry practice is to uniformly add slots to wide and long copper interconnect lines, this to achieve improved CMP results. These slots, typically having a wi |
| 7385249 |
Transistor structure and integrated circuit |
June 10, 2008 |
| A process for forming a conductive gate structure for a sub-0.25 MOSFET technology, has been developed. The process features a conductive gate structure defined from a composite polysilicon or amorphous layer, which in turn is obtained via a dual deposition procedure. The first, or u |
| 7371629 |
N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications |
May 13, 2008 |
| A method is provided for improving Idsat in NMOS and PMOS transistors. A silicon nitride etch stop layer is deposited by a PECVD technique on STI and silicide regions and on sidewall spacers during a MOSFET manufacturing scheme. A dielectric layer is formed on the nitride and then co |
| 7364836 |
Dual damascene process |
April 29, 2008 |
| A method of photoresist processing includes forming a first photoresist layer over composite layers of dielectric insulation and a top insulating layer and patterning a via hole pattern in the first photoresist layer by exposing to radiation of a first sensitivity. A second photoresist l |
| 7359759 |
Method and system for virtual metrology in semiconductor manufacturing |
April 15, 2008 |
| Provided are a method and a system for virtual metrology in semiconductor manufacturing. Process data and metrology data are received. Prediction data is generated based on the process data and metrology data using a learning control model. The system for virtual metrology in a fabricati |
| 7358612 |
Plasma treatment at film layer to reduce sheet resistance and to improve via contact resistance |
April 15, 2008 |
| A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed over the plasma-treated |
| 7358571 |
Isolation spacer for thin SOI devices |
April 15, 2008 |
| A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa. |
| 7357838 |
Relaxed silicon germanium substrate with low defect density |
April 15, 2008 |
| A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe is provided. |
| 7356656 |
Skew free control of a multi-block SRAM |
April 8, 2008 |
| A multi-block SRAM memory system is described where a single global clock pulse is distributed to each memory block from the central control. At each SRAM memory block a local signal generator uses the globally distributed clock pulse to generate the required memory control pulse sig |
| 7356550 |
Method for real time data replication |
April 8, 2008 |
| A computer-based method of data replication of data in a programmable computer system having an ISAM database and a transaction log file, with the ISAM database having fields of tables and the transaction log file maintaining all files transactions of the ISAM database, comprising the |
| 7356378 |
Method and system for smart vehicle route selection |
April 8, 2008 |
| In one aspect a factory automation system for a wafer fab is provided. The factory automation system comprises: a manufacturing execution system ("MES") for providing lot information; a material control system ("MCS") for providing dynamic traffic information; an automated material handl |
| 7354847 |
Method of trimming technology |
April 8, 2008 |
| A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature having a width w.sub.1 |
| 7353077 |
Methods for optimizing die placement |
April 1, 2008 |
| A method of optimizing die placement on a wafer having an alignment mark with a computing system includes arranging a plurality of fields on the wafer in a first position. Dummies are inserted between at least one arranged field and the alignment mark and inserted adjacent to the wafer |
| 7351994 |
Noble high-k device |
April 1, 2008 |
| At least one high-k device, and a method for forming the at least one high-k device, comprising the following. A structure having a strained substrate formed thereover. The strained substrate comprising at least an uppermost strained-Si epi layer. At least one dielectric gate oxide p |
| 7351936 |
Method and apparatus for preventing baking chamber exhaust line clog |
April 1, 2008 |
| A method and apparatus involve providing a supply of nitrogen gas, heating the supply of nitrogen gas to a temperature, and ejecting the heated nitrogen gas through the exhaust line of the baking chamber on a periodic basis. The temperature is between a temperature of the hot plate and a |
| 7345524 |
Integrated circuit with low power consumption and high operation speed |
March 18, 2008 |
| An integrated circuit includes a functional circuit module operating at a voltage range between a first voltage level and a second voltage level lower than the first voltage level. A power supply switch module, coupled between the functional circuit module and one or more power supplies, |
| 7339253 |
Retrograde trench isolation structures |
March 4, 2008 |
| Methods are provided for making retrograde trench isolation structures with improved electrical insulation properties. One method comprises the steps of: forming a retrograde trench in a silicon substrate, and forming a layer of silicon oxide on the walls of the trench by thermal oxidati |
| 7333173 |
Method to simplify twin stage scanner OVL machine matching |
February 19, 2008 |
| Multiple scanner or stepper machines are provided. A photoresist layer is coated on a monitor wafer. The photoresist layer is exposed through a mask pattern on a first of the multiple machines. The mask pattern is shifted by an offset and the photoresist layer is exposed through the |
| 7303841 |
Repair of photolithography masks by sub-wavelength artificial grating technology |
December 4, 2007 |
| A method is disclosed for repairing mask damage defects. After determining topographical information of a defect on a mask, one or more grating repair specifications are determined based on an optical simulation using the topographical information. One or more artificial grating areas ar |
| 7301229 |
Electrostatic discharge (ESD) protection for integrated circuit packages |
November 27, 2007 |
| An integrated circuit package includes a package substrate with a plurality of pins coupled to a semiconductor chip having a plurality of bond pads, some of which are ic bond pads coupled to an integrated circuit formed on the semiconductor chip and others of which are floating bond |
| 7291557 |
Method for forming an interconnection structure for ic metallization |
November 6, 2007 |
| A method for forming an interconnection structure in an integrated circuit includes the following steps. A dielectric layer is formed on a semiconductor substrate. An opening is formed on the dielectric layer. A barrier layer is formed over inner walls of the opening and the dielectr |
| 7279428 |
Method of preventing photoresist residues |
October 9, 2007 |
| A method to prevent photoresist residues formed in an aperture is provided. The method includes using a halogen-containing plasma treatment before the aperture is filled with a photoresist. Due to the halogen-containing plasma treatment, amine components on the sidewalls of a via or |
| 7274544 |
Gate-coupled ESD protection circuit for high voltage tolerant I/O |
September 25, 2007 |
| The present disclosure is directed toward electrostatic device protection for semiconductor devices. A circuit for providing electro-static discharge (ESD) protection for a semiconductor circuit may comprise a first circuit coupled to a voltage bus and to the gate of a first transist |
| 7269063 |
Floating gate memory with split-gate read transistor and split gate program transistor memory ce |
September 11, 2007 |
| Variations in memory array and cell configuration are shown, which eliminate punch-through disturb, reverse-tunnel. Several configurations are shown which range from combined and separate source lines for each row of cells, a two transistor cell containing a read transistor and a pro |
| 7267600 |
Polishing apparatus |
September 11, 2007 |
| Apparatus for polishing are provided. An apparatus comprises a fluid controller, a polishing apparatus and a fluid interface membrane. The fluid controller is fluidly coupled to the polishing apparatus by way of at least one conduit. The fluid interface membrane is disposed within at |
| 7262067 |
Method for conductive film quality evaluation |
August 28, 2007 |
| A method for monitoring copper film quality and for evaluating the annealing efficiency of a copper annealing process includes measuring hardness of a copper film formed on a substrate before and after annealing and comparing the hardness measurement results. The measurements can be |
| 7259850 |
Approach to improve ellipsometer modeling accuracy for solving material optical constants N & K |
August 21, 2007 |
| A method of determining optical constants n and k for a film on a substrate is described. Optical measurements are preferably performed with an integrated optical measurement system comprising a reflectometer, spectral ellipsometer, and broadband spectrometer such as an Opti-Probe se |
| 7253114 |
Self-aligned method for defining a semiconductor gate oxide in high voltage device area |
August 7, 2007 |
| A method is provided for forming at least three devices with different gate oxide thicknesses and different associated operating voltages, in the same integrated circuit device. The method includes forming a plurality of gate oxides with different thicknesses in high voltage and low |
| 7248076 |
Dual-voltage three-state buffer circuit with simplified tri-state level shifter |
July 24, 2007 |
| A dual-voltage three-state buffer circuit controls a post driver circuit to operate in a three-state mode and includes a tri-state logic control module operated under a low supply voltage, a level shifter for receiving one or more inputs from the tri-state logic control module and operat |
