| Patent Number |
Title Of Patent |
Date Issued |
| 7616416 |
System to protect electrical fuses |
November 10, 2009 |
| A method and system is disclosed for protecting electrical fuse circuitry. A electrical fuse circuit with electrostatic discharge (ESD) protection has at least one electrical fuse, a programming device coupled in series with the electrical fuse having at least a transistor for receiving |
| 7615487 |
Power delivery package having through wafer vias |
November 10, 2009 |
| An integrated circuit chip package and a method of manufacture thereof are provided. In one embodiment, the integrated circuit chip package comprises a semiconductor die having power and ground routings, a plurality of through wafer vias disposed within the semiconductor die, the thr |
| 7614030 |
Scattering bar OPC application method for mask ESD prevention |
November 3, 2009 |
| A method for reducing ESD on scattering bars in forming a mask containing a target pattern is provided. In one embodiment, the target pattern comprising features to be imaged onto a substrate is obtained. The mask is modified to include at least one scattering bar, the at least one s |
| 7613054 |
SRAM device with enhanced read/write operations |
November 3, 2009 |
| An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for acce |
| 7612638 |
Waveguides in integrated circuits |
November 3, 2009 |
| A waveguide in semiconductor integrated circuit is disclosed, the waveguide comprises a horizontal first metal plate, a horizontal second metal plate above the first metal plate, separated by an insulation material, and a plurality of metal vias positioned in two parallel lines, runn |
| 7611589 |
Methods of spin-on wafer cleaning |
November 3, 2009 |
| A method for spin-on wafer cleaning. The method comprises controlling spin speed and vertical water jet pressure. The vertical jet pressure and the spin speed are substantially maintained in inverse proportion. Wafer spin speed is between 50 to 1200 rpm. Vertical wafer jet pressure is be |
| 7608889 |
Lateral diffusion metal-oxide-semiconductor structure |
October 27, 2009 |
| A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semic |
| 7607132 |
Process scheduling system and method |
October 20, 2009 |
| A process scheduling system and method. The system includes a fetch module, a timing scheduling module and a trigger module. The fetch module fetches resource status data of at least one resource item of an application system periodically. The timing scheduling module dynamically det |
| 7606724 |
Demand dispatch system and method |
October 20, 2009 |
| A demand dispatch system to provide stable fabrication loading. The system includes a risk database recording risk information for a demand and an allocation planning module. The allocation planning module receives the demand, divides the demand into a low risk demand and a high risk dem |
| 7606061 |
SRAM device with a power saving module controlled by word line signals |
October 20, 2009 |
| An SRAM device include: a latch unit for retaining data; one or more pass gate transistors controlled by a word line for coupling the latch unit to a bit line and a complementary bit line; and a power saving module coupled to the latch unit for raising a source voltage of the latch unit |
| 7605577 |
Start-up circuit for a bandgap circuit |
October 20, 2009 |
| A startup circuit operating with a bandgap circuit having a predetermined node with a current change proportional to temperature change and a current source connected to the predetermined node comprising: a controllable current switch connected between the predetermined node and a co |
| 7602065 |
Seal ring in semiconductor device |
October 13, 2009 |
| A semiconductor device includes a first circuit, a first seal ring and at least one first notch. The first seal ring surrounds the first circuit. The first notch cuts the first seal ring. Specifically, the first notch includes an inner opening, an outer opening and a connecting groove. T |
| 7602037 |
High voltage semiconductor devices and methods for fabricating the same |
October 13, 2009 |
| An exemplary embodiment of a semiconductor device capable of high-voltage operation includes a substrate with a well region therein. A gate stack with a first side and a second side opposite thereto, overlies the well region. Within the well region, a doped body region includes a channel |
| 7602006 |
Semiconductor flash device |
October 13, 2009 |
| A flash memory device includes a floating gate made of a multi-layered structure. The floating gate includes a hetero-pn junction which serves as a quantum well to store charge in the floating gate, thus increasing the efficiency of the device, allowing the device to be operable using |
| 7600165 |
Error control coding method and system for non-volatile memory |
October 6, 2009 |
| Methods and systems for improving repairing efficiency in non-volatile memory. Repairing data may be read from an information array associated with the non-volatile memory. The repairing data is generally read to a volatile latch associated with the non-volatile memory. An error corr |
| 7599212 |
Method and apparatus for high-efficiency operation of a dynamic random access memory |
October 6, 2009 |
| The disclosure generally relates to a method and apparatus for reading and writing information to a memory cell in communication with a word line and one of a bit line or a complementary bit line. A method according to one embodiment includes: equalizing the bit line and the complementar |
| 7598176 |
Method for photoresist stripping and treatment of low-k dielectric material |
October 6, 2009 |
| A plasma processing operation uses a gas mixture of N.sub.2 and H.sub.2 to both remove a photoresist film and treat a low-k dielectric material. The plasma processing operation prevents degradation of the low-k material by forming a protective layer on the low-k dielectric material. Carb |
| 7597787 |
Methods and apparatuses for electrochemical deposition |
October 6, 2009 |
| Methods and apparatuses for electrochemically depositing a metal layer onto a substrate. An electrochemical deposition apparatus comprises a substrate holder assembly including a substrate chuck and a relatively soft cathode contact ring. The cathode contact ring comprises an inner p |
| 7596737 |
System and method for testing state retention circuits |
September 29, 2009 |
| This invention discloses a system and method for testing a plurality of state retention circuits in an integrated circuit (IC) chip, that comprises a built-in test circuit configured to invoke a clock, a save and a restore signal, and a plurality of serially connected data latches re |
| 7594198 |
Ultra fine pitch I/O design for microchips |
September 22, 2009 |
| A microchip includes at least one I/O area surrounding at least one core circuit area. The I/O area further includes a first I/O cell having at least one first post-driver device connected to a first I/O pad; a second I/O cell having at least one second post-driver device connected to a |
| 7592891 |
Planar spiral inductor structure having enhanced Q value |
September 22, 2009 |
| Within a method for fabricating an inductor structure there is first provided a substrate. There is then formed over the substrate a planar spiral conductor layer to form a planar spiral inductor, wherein a successive series of spirals within the planar spiral conductor layer is form |
| 7592649 |
Memory word lines with interlaced metal layers |
September 22, 2009 |
| A memory device with improved word line structure is disclosed. The memory device includes a plurality of polysilicon strips substantially parallel to each other on the substrate, the plurality of polysilicon strips arranged in two interleaved groups of a first group and a second group. |
| 7592619 |
Epitaxy layer and method of forming the same |
September 22, 2009 |
| A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si--Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to |
| 7592220 |
Capacitance process using passivation film scheme |
September 22, 2009 |
| In accordance with the objectives of the invention a new method and structure is provided for the creation of a capacitor. A contact pad and a lower capacitor plate have been provided over a substrate. Under the first embodiment of the invention, a layer of etch stop material, serving |
| 7592199 |
Method for forming pinned photodiode resistant to electrical leakage |
September 22, 2009 |
| A method is provided for reducing or eliminating leakage between a pinned photodiode and shallow trench isolation structure fabricated therewith while optimizing the sensitivity of the photodiode. An N+ region is implanted in a P-type substrate and a P-type well separates the N+ region |
| 7589005 |
Methods of forming semiconductor structures and systems for forming semiconductor structures |
September 15, 2009 |
| A method and system for forming a semiconductor structure includes forming at least one material layer over a substrate. At least one portion of the material layer is etched with at least one first precursor, thereby defining at least one material pattern. Charges attached to the materia |
| 7587456 |
Operation system and method of workflow integrated with a mail platform and web applications |
September 8, 2009 |
| Operation system and method of workflow are provided. The system includes a mail platform and a web application. The mail platform receives an email including an application identification of the web application, a target URL corresponding to a target, and at least one recipient. The |
| 7587293 |
Semiconductor CP (circuit probe) test management system and method |
September 8, 2009 |
| A system and method for semiconductor CP (circuit probe) test management. A control request message is received from a client computer, directing alignment of a probe unit or a wafer in a prober, attachment of a probe pin of the probe unit on a specific area of the wafer, and subsequent |
| 7586147 |
Butted source contact and well strap |
September 8, 2009 |
| A butted contact structure forming a source contact electrically connecting a voltage node and a well region and method for forming the same, the butted contact structure including an active region having a well region disposed adjacent an electrical isolation region on a semiconduct |
| 7586145 |
EEPROM flash memory device with jagged edge floating gate |
September 8, 2009 |
| An EEPROM flash memory device having a floating gate electrode enabling a reduced erase voltage and method for forming the same, the floating gate electrode including an outer edge portion including multiple charge transfer pointed tips. |
| 7585711 |
Semiconductor-on-insulator (SOI) strained active area transistor |
September 8, 2009 |
| A selectively strained MOS device such as selectively strained PMOS device making up an NMOS and PMOS device pair without affecting a strain in the NMOS device the method including providing a semiconductor substrate comprising a lower semiconductor region, an insulator region overlying |
| 7583502 |
Method and apparatus for increasing heat dissipation of high performance integrated circuits (IC |
September 1, 2009 |
| A heat sink is presented for dissipating heat from an integrated circuit (IC). The heat sink is made of a heat conductive material having a generally planar shape and adapted to receive an IC chip on a bottom surface and adapted to be in thermal connection with the IC chip. The heat |
| 7582557 |
Process for low resistance metal cap |
September 1, 2009 |
| An exemplary method includes: providing a substrate with exposed metal and dielectric surfaces, performing a reducing process on the metal and dielectric surfaces, and transferring the substrate in an inert or reducing ambient to a chamber for that is used for selective metal layer d |
| 7582494 |
Device structures for reducing device mismatch due to shallow trench isolation induced oxides st |
September 1, 2009 |
| A circuit and method are disclosed for reducing device mismatch due to trench isolation related stress. One or more extended active regions are formed on the substrate, wherein the active regions being extended from one or more ends thereof, and one or more operational devices are placed |
| 7579918 |
Clock generator with reduced electromagnetic interference for DC-DC converters |
August 25, 2009 |
| A clock generator includes a current source for generating a constant current; a current mirror coupled between a supply voltage and the current source for generating a mirror current equal to the constant current multiplied by a predetermined value; and a charge control module coupl |
| 7579121 |
Optical proximity correction photomasks |
August 25, 2009 |
| An optical proximity correction photomask comprises a transparent substrate, a main feature having a first transmitivity disposed on the transparent substrate and at least one assist feature having a second transmitivity disposed to each side of the main feature and on the transparen |
| 7577056 |
System and method for using a DLL for signal timing control in a eDRAM |
August 18, 2009 |
| The present invention discloses an embedded dynamic random access memory (eDRAM) comprising a clock signal, at least one delay-locked loop (DLL) circuit coupled to the clock signal and configured to generate a plurality of control signals each having a predetermined delay from the cl |
| 7577052 |
Power switching circuit |
August 18, 2009 |
| A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to |
| 7577040 |
Dual port memory device with reduced coupling effect |
August 18, 2009 |
| A dual port SRAM cell includes at least one pair of cross-coupled inverters connected between a power line and complementary power line. A number of pass gate transistors connect the cross-coupled inverters to a first bit line, a first complementary bit line, a second bit line, and a |
| 7573138 |
Stress decoupling structures for flip-chip assembly |
August 11, 2009 |
| A stress decoupling structure provided underneath the under-ball-metallurgy (UBM) pads of a flip-chip bonding integrated circuit (IC) chip enhances the cyclic fatigue life of the solder joints formed by the solder bumps on the IC chip. The stress decoupling structure is formed from a |
| 7566935 |
ESD structure without ballasting resistors |
July 28, 2009 |
| An electrostatic discharge (ESD) structure connected to a bonding pad in an integrated circuit comprising: a P-type substrate with one or more first P+ regions connected to a low voltage supply (GND), a first Nwell formed in the P-type substrate, one or more second P+ regions disposed |
| 7566525 |
Method for forming an anti-etching shielding layer of resist patterns in semiconductor fabricati |
July 28, 2009 |
| A method is disclosed for forming a photoresist pattern with enhanced etch resistance on a semiconductor substrate. A photoresist pattern is first formed on the substrate. A silicon-containing polymer layer is deposited over the photoresist pattern on the substrate. A thermal treatment i |
| 7565635 |
SiP (system in package) design systems and methods |
July 21, 2009 |
| SiP design systems and methods. The system comprises a system partitioning module, a subsystem integration module, a physical design module, and an analysis module. The system partitioning module partitions a target system into subsystem partitions according to partition criteria. The |
| 7564709 |
Method and system for utilizing DRAM components in a system-on-chip |
July 21, 2009 |
| A system-on-chip semiconductor circuit includes a logic circuit having at least one first transistor with a thin gate dielectric, at least one dynamic random access memory cell coupled with the logic circuit having at least one storage capacitor and at least one thick gate dielectric |
| 7564295 |
Automatic bias circuit for sense amplifier |
July 21, 2009 |
| The present invention discloses a bias circuit for a sense amplifier having a device under sensing, the device under sensing having an un-programmed state and a programmed state, the bias circuit comprises at least one first branch having at least one first device formed substantiall |
| 7564287 |
High voltage tolerant input buffer |
July 21, 2009 |
| An input buffer protection circuit is disclosed which comprises a NMOS transistor with a source, drain and gate coupled to an input terminal of the input buffer, a pad and a chip peripheral positive power supply voltage (VDDP), respectively, and a PMOS transistor with a source, drain |
| 7564105 |
Quasi-plannar and FinFET-like transistors on bulk silicon |
July 21, 2009 |
| The types of quasi-planar CMOS and FinFET-like transistor devices on a bulk silicon substrate are disclosed. A first device has a doped and recessed channel formed in a shallow trench sidewall. A second device has a doped, recessed channel and has a plurality of edge-fins juxtaposed on |
| 7563719 |
Dual damascene process |
July 21, 2009 |
| A dual damascene process. A first photoresist layer with a first opening corresponding to a trench pattern is formed on a dielectric layer. A second photoresist layer with a second opening corresponding to a via pattern smaller then the trench pattern is formed on the first photoresi |
| 7563675 |
Ladder poly etching back process for word line poly planarization |
July 21, 2009 |
| A method is disclosed for etching a polysilicon material in a manner that prevents formation of an abnormal polysilicon profile. The method includes providing a substrate with a word line and depositing a polysilicon layer over said substrate and word line. An organic bottom antirefl |
| 7557423 |
Semiconductor structure with a discontinuous material density for reducing eddy currents |
July 7, 2009 |
| A semiconductor structure includes an inductor; and a semiconductor substrate underlying the inductor, having a discontinuous material density across a plane underneath and in parallel with the inductor, thereby reducing eddy currents induced by an electrical current flowing through |
