| Patent Number |
Title Of Patent |
Date Issued |
| RE40925 |
Methods for automatically pipelining loops |
September 29, 2009 |
| A method and an apparatus for creating a representation of a circuit with a pipelined loop from an HDL source code description. It infers a circuit including a pipelined loop which has cycle level simulation behavior matching that of the source HDL. Loop carry dependencies and memory and |
| 7627844 |
Methods and apparatuses for transient analyses of circuits |
December 1, 2009 |
| Methods and apparatuses for transient analyses of a circuit using a hierarchical approach. In one embodiment, the cells are grouped locally on the power supply network according to average power dissipation. A time varying current of each cell group is estimated using a probabilistic |
| 7620917 |
Methods and apparatuses for automated circuit design |
November 17, 2009 |
| Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a logic function feeding a carry chain is implemented through extending the carry chain and through using the extended portion of the carry chain. In one aspect of an embodiment, control/non |
| 7617478 |
Flash-based anti-aliasing techniques for high-accuracy high efficiency mask synthesis |
November 10, 2009 |
| One embodiment of the present invention provides a system that converts a non-bandlimited pattern layout into a band-limited pattern image to facilitate simulating an optical lithography process. During operation, the system receives the non-bandlimited pattern layout which comprises |
| 7617474 |
System and method for providing defect printability analysis of photolithographic masks with job |
November 10, 2009 |
| Serious defects on a mask can compromise the functionality of the integrated circuits formed on the wafer. Nuisance defects, which do not affect the functionality, waste expensive resources. A defect analysis tool with job-based automation can accurately and efficiently determine def |
| 7617468 |
Method for automatic maximization of coverage in constrained stimulus driven simulation |
November 10, 2009 |
| A computer increases coverage in simulation of a design of a circuit by processing goals for coverage differently depending on whether or not the goals are on input signals of the circuit. Specifically, goals on input signals are used to automatically formulate constraints ("directly |
| 7617464 |
Verifying an IC layout in individual regions and combining results |
November 10, 2009 |
| When performing rule checking locally within any given region of a layout of an integrated circuit, certain data is generated to be checked globally, regardless of boundaries (hereinafter "to-be-globally-checked" data). The to-be-globally-checked data, resulting from execution of a g |
| 7613599 |
Method and system for virtual prototyping |
November 3, 2009 |
| An integrated design environment (IDE) is disclosed for forming virtual embedded systems. The IDE includes a design language for forming finite state machine models of hardware components that are coupled to simulators of processor cores, preferably instruction set accurate simulator |
| 7605449 |
Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation material |
October 20, 2009 |
| By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a "corrugated substrate"), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be r |
| 7602964 |
Method and apparatus for detection of failures in a wafer using transforms and cluster signature |
October 13, 2009 |
| Detecting spatial failures in a wafer can be performed quickly and accurately by using transformations and cluster signature analysis. For this technique, a system can receive failure coordinates for the wafer, wherein each failure coordinate indicates a spatial failure. A failure ar |
| 7600207 |
Stress-managed revision of integrated circuit layouts |
October 6, 2009 |
| Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce |
| 7596733 |
Dynamically reconfigurable shared scan-in test architecture |
September 29, 2009 |
| A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every sh |
| 7594213 |
Method and apparatus for computing dummy feature density for chemical-mechanical polishing |
September 22, 2009 |
| One embodiment of the present invention provides a system that computes dummy feature density for a CMP (Chemical-Mechanical Polishing) process. Note that the dummy feature density is used to add dummy features to a layout to reduce the post-CMP topography variation. During operation, th |
| 7594211 |
Methods and apparatuses for reset conditioning in integrated circuits |
September 22, 2009 |
| Embodiments of the present invention disclose methods and apparatuses to reduce metastability problem related to propagation delay of reset signals in integrated circuits, with preferred applications in automatic physical synthesis for RTL (register transfer level) netlist. In an emb |
| 7587718 |
Method and apparatus for enforcing a resource-usage policy in a compute farm |
September 8, 2009 |
| One embodiment of the present invention provides a system that enforces a resource-usage policy in a compute farm. During operation, the system can receive etiquette rules which include resource-usage rules and corrective-action rules. Resource-usage rules can specify situations in w |
| 7587691 |
Method and apparatus for facilitating variation-aware parasitic extraction |
September 8, 2009 |
| One embodiment of the present invention provides a system for determining an electrical property for an interconnect layer. During operation, the system receives interconnect technology data which includes nominal parameter values for a first interconnect layer, and parameter-variation |
| 7586998 |
Method and apparatus for receiver pulse response determination |
September 8, 2009 |
| A pulse response for a receiver, as an array PR, is found from the receiver's symbol stream.For a continuous stream of arbitrary data, a value of the array PR[k] can be determined from the signal levels of the symbols received. The stream of received data is input to a FIFO. Between |
| 7585600 |
Method and apparatus for performing target-image-based optical proximity correction |
September 8, 2009 |
| A system that performs target-image-based optical proximity correction on masks that are used to generate an integrated circuit is presented. The system operates by first receiving a plurality of masks that are used to expose features on the integrated circuit. Next, the system computes |
| 7585595 |
Phase shift mask including sub-resolution assist features for isolated spaces |
September 8, 2009 |
| A method extends the use of phase shift techniques to complex layouts, and includes identifying a pattern, and automatically mapping the phase shifting regions for implementation of such features. The pattern includes small features having a dimension smaller than a first particular |
| 7584450 |
Method and apparatus for using a database to quickly identify and correct a manufacturing proble |
September 1, 2009 |
| One embodiment provides a system for using a database to quickly identify a manufacturing problem area in a layout. During operation, the system receives a first check-figure which identifies a first area in a first layout, wherein the first area is associated with a first feature. Next, |
| 7584438 |
Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array |
September 1, 2009 |
| An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as chann |
| 7581197 |
Relative positioning of circuit elements in circuit design |
August 25, 2009 |
| Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed, routed, and optimized circuits design obeys relative positioning rules of a set of the circuit |
| 7565001 |
System and method of providing mask defect printability analysis |
July 21, 2009 |
| A simulated wafer image of a physical mask and a defect-free reference image are used to generate a severity score for each defect, thereby giving a customer meaningful information to accurately assess the consequences of using a mask or repairing that mask. The defect severity score |
| 7562319 |
Displacing edge segments on a fabrication layout based on proximity effects model amplitudes for |
July 14, 2009 |
| Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is |
| 7560201 |
Patterning a single integrated circuit layer using multiple masks and multiple masking layers |
July 14, 2009 |
| A multiple mask and a multiple masking layer technique can be used to pattern a single IC layer. A resolution enhancement technique can be used to define one or more fine-line patterns in a first masking layer, wherein each fine-line feature is sub-wavelength. Moreover, the pitch of |
| 7557009 |
Process for controlling performance characteristics of a negative differential resistance (NDR) |
July 7, 2009 |
| A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (V.sub.NDR) and related parameters. The processes are based on conventional semiconductor manufacturing operations so that an NDR device |
| 7552409 |
Engineering change order process optimization |
June 23, 2009 |
| A method for reaching signoff closure in an ECO (engineering change order) process involves the use of violation context data from the signoff tool as the basis for design layout modifications in an implementation tool. The violation context data includes violation information other than |
| 7546567 |
Method and apparatus for generating a variation-tolerant clock-tree for an integrated circuit ch |
June 9, 2009 |
| One embodiment of the present invention relates to a process that generates a clock-tree on an integrated circuit (IC) chip. During operation, the process starts by receiving a placement for a chip layout, where the placement includes a set of registers at fixed locations in the chip |
| 7546566 |
Method and system for verification of multi-voltage circuit design |
June 9, 2009 |
| Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the |
| 7546558 |
Method and apparatus for determining a process model that uses feature detection |
June 9, 2009 |
| One embodiment can provide a system for determining a process model that models an effect of one or more semiconductor manufacturing processes. During operation, the system can receive a test layout. Next, the system can receive empirical data which is obtained using a process that i |
| 7546500 |
Slack-based transition-fault testing |
June 9, 2009 |
| A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating |
| 7546227 |
Segmentation and interpolation of current waveforms |
June 9, 2009 |
| A method for generating a linear piecewise representation of a driver output current signal includes segmenting the driver output current signal such that an integral of each segment matches an actual voltage change in corresponding portion of an associated output voltage signal (wit |
| 7545886 |
Method and apparatus for eye-opening based optimization |
June 9, 2009 |
| An eye opening measurement technique, that does not interrupt a receiver's normal operation, is used as a metric for optimizing any selected parameters of the receiver's operation. If eye opening size decreases, as a result of a change to a receiver parameter, the polarity for stepwise |
| 7545860 |
System and method of equalization of high speed signals |
June 9, 2009 |
| In one aspect, the present invention is directed to a technique of, and system for enhancing the performance of high-speed digital communications through a communications channel, for example a backplane. In this aspect of the present invention, a transmitter includes equalization circui |
| 7543255 |
Method and apparatus to reduce random yield loss |
June 2, 2009 |
| One embodiment of the present invention provides a system that reduces random yield loss. During operation, the system can receive a design layout. The system may also receive weighting factors that are associated with the particle densities in the metal regions and the empty regions. |
| 7543254 |
Method and apparatus for fast identification of high stress regions in integrated circuit struct |
June 2, 2009 |
| Roughly described, high-stress volumetric regions of an integrated circuit structure are predicted by first scanning one or more layout layers to identify planar regions of high 2-dimensional stress, and then performing the much more expensive 3-dimensional stress analysis only on volume |
| 7542891 |
Method of correlating silicon stress to device instance parameters for circuit simulation |
June 2, 2009 |
| Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard, stress-sensitive, transistor model is used to develop a mathematical relationship between the f |
| 7537866 |
Patterning a single integrated circuit layer using multiple masks and multiple masking layers |
May 26, 2009 |
| A multiple mask and a multiple masking layer technique can be used to pattern a single IC layer. A resolution enhancement technique can be used to define one or more fine-line patterns in a first masking layer, wherein each fine-line feature is sub-wavelength. Moreover, the pitch of |
| 7536658 |
Power pad synthesizer for an integrated circuit design |
May 19, 2009 |
| A power pad synthesizer automatically proposes locations of pads that are to carry power in an integrated circuit design. Specifically, a computer is programmed to prepare the plan in at least two stages as follows. In a first stage, a number of pads are proposed around a periphery of th |
| 7534531 |
Full phase shifting mask in damascene process |
May 19, 2009 |
| A full phase shifting mask (FPSM) can be advantageously used in a damascene process for hard-to-etch metal layers. Because the FPSM can be used with a positive photoresist, features on an original layout can be replaced with shifters on a FPSM layout. Adjacent shifters should be of o |
| 7528465 |
Integrated circuit on corrugated substrate |
May 5, 2009 |
| By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a "corrugated substrate"), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be r |
| 7523428 |
Hierarchical signal integrity analysis using interface logic models |
April 21, 2009 |
| Performing signal integrity (SI) analysis on integrated circuit designs is becoming increasingly important as these designs increase in size and complexity. Dividing a design into blocks can simplify the resulting analysis. Additionally, such blocks can be replaced with timing models, |
| 7523423 |
Method and apparatus for production of data-flow-graphs by symbolic simulation |
April 21, 2009 |
| One embodiment of the present invention provides a system that produces a non-canonical data flow graph (DFG) structure by symbolic simulation of an input representation for a high-level model (HLM). This system considers all scenarios for flow-of-control for the HLM, and represents |
| 7523027 |
Visual inspection and verification system |
April 21, 2009 |
| A method and apparatus for inspecting a photolithography mask for defects is provided. The inspection method comprises providing a defect area image to an image simulator wherein the defect area image is an image of a portion of a photolithography mask, and providing a set of lithography |
| 7522659 |
Universal serial bus (USB) 2.0 legacy full speed and low speed (FS/LS) mode driver |
April 21, 2009 |
| A Universal Serial Bus (USB) 2.0 transceiver includes a legacy full speed and low speed (FS/LS) USB driver that includes multiple output stages. The multiple output stages are connected in parallel to an output terminal. By sequentially providing the USB data to the multiple output s |
| 7521966 |
USB 2.0 transmitter using only 2.5 volt CMOS devices |
April 21, 2009 |
| A USB transmitter 3.3V output stage includes a PMOS cascode transistor connected between a PMOS pullup transistor and a USB port data pin, an NMOS cascode transistor connected between an NMOS pulldown transistor and the data pin, and an output driver circuit that generates a pullup signa |
| 7512912 |
Method and apparatus for solving constraints for word-level networks |
March 31, 2009 |
| The following techniques for word-level networks are presented: constraints solving, case-based learning and bit-slice solving. Generation of a word-level network to model a constraints problem is presented. The networks utilized have assigned, to each node, a range of permissible va |
| 7509624 |
Method and apparatus for modifying a layout to improve manufacturing robustness |
March 24, 2009 |
| One embodiment of the present invention provides a system that modifies a layout to improve manufacturing robustness. During operation, the system receives a layout. The system then selects a segment in the layout. Next, the system determines a target location in the proximity of the seg |
| 7509622 |
Dummy filling technique for improved planarization of chip surface topography |
March 24, 2009 |
| The use of smooth post-ECP topography (instead of final chip topography) as an objective during dummy filling enables a computationally efficient model-based dummy filling solution for copper while maintaining solution quality. A layout can be divided into tiles and the "case" of each ti |
| 7509621 |
Method and apparatus for placing assist features by identifying locations of constructive and de |
March 24, 2009 |
| One embodiment of the present invention provides a system that determines a location in a layout to place an assist feature. During operation, the system receives a layout of an integrated circuit. Next, the system selects an evaluation point in the layout. The system then chooses a |
