| Patent Number |
Title Of Patent |
Date Issued |
| 7622389 |
Selective contact formation using masking and resist patterning techniques |
November 24, 2009 |
| A method for manufacturing a semiconductor device including selective conductive contacts includes the step of depositing a resist over first and second memory device components, each of the first and second components comprising junctions formed in the substrate and a gate formed on |
| 7622373 |
Memory device having implanted oxide to block electron drift, and method of manufacturing the sa |
November 24, 2009 |
| A memory device includes a substrate, a first gate stack overlying the substrate, a second gate stack overlying the substrate and spaced apart from the first gate stack, an oxide region formed at a first depth within the substrate and between the first and second gate stacks, and an |
| 7622067 |
Apparatus and method for manufacturing a semiconductor device |
November 24, 2009 |
| An apparatus for manufacturing a semiconductor device includes an upper mold (21), a lower mold (22), and a plate (30, 130, 230) that includes at least one cavity (31) that receives resin and defines an outer shape and a thickness of a resin sealing portion, and a gate (32) through which |
| 7619934 |
Method and apparatus for adaptive memory cell overerase compensation |
November 17, 2009 |
| A method and apparatus are provided for adaptive memory cell overerase compensation. A semiconductor memory device (100) is provided for performing the adaptively compensating erase verify operation (500, 600). The memory device (100) includes at least one word line (402). One or mor |
| 7619932 |
Algorithm for charge loss reduction and Vt distribution improvement |
November 17, 2009 |
| Methods and systems for accurately programming or erasing one or more memory cells on a selected wordline of a memory device are provided. In one embodiment, the memory device comprises a memory array, a threshold voltage measuring component configured to measure a threshold voltage of |
| 7613044 |
Method and apparatus for high voltage operation for a high performance semiconductor memory devi |
November 3, 2009 |
| A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected |
| 7613042 |
Decoding system capable of reducing sector select area overhead for flash memory |
November 3, 2009 |
| Methods and apparatus are disclosed for erasing memory cells in a virtual ground memory core, wherein a row decoder apparatus employs a protective voltage to wordlines of a sector of cells while concurrently providing an erase voltage to selected wordlines of the same physical sector. De |
| 7608855 |
Polymer dielectrics for memory element array interconnect |
October 27, 2009 |
| Disclosed are semiconductor devices containing a polymer dielectric and at least one active device containing an organic semiconductor material and a passive layer. Also disclosed are semiconductor devices further containing a conductive polymer. Such devices are characterized by light |
| 7606085 |
Semiconductor device and control method of the same |
October 20, 2009 |
| The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 |
| 7606068 |
Memory with a core-based virtual ground and dynamic reference sensing scheme |
October 20, 2009 |
| A core-based multi-bit memory (400) having a dual-bit dynamic referencing architecture (408, 410) fabricated on the memory core (401). A first reference array (408) and a second reference array (410) are fabricated on the memory core (401) such that a reference cell pair (185) comprising |
| 7605616 |
Voltage detector circuit |
October 20, 2009 |
| A voltage detection circuit for accurately detecting a voltage that is unaffected by fluctuation due to variations in transistor characteristics and threshold voltage. The voltage detection circuit includes a reference current generating section and a detecting section. The reference cur |
| 7605457 |
Semiconductor device and method of manufacturing the same |
October 20, 2009 |
| The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side |
| 7602639 |
Reading electronic memory utilizing relationships between cell state distributions |
October 13, 2009 |
| Providing distinction between overlapping state distributions of one or more multi cell memory devices is described herein. By way of example, a system can include a calculation component that can perform a mathematical operation on an identified, non-overlapped bit distribution and |
| 7602067 |
Hetero-structure variable silicon rich nitride for multiple level memory flash memory device |
October 13, 2009 |
| Charge storage stacks containing hetero-structure variable silicon richness nitride for memory cells and methods for making the charge storage stacks are provided. The charge storage stack can contain a first insulating layer on a semiconductor substrate; n charge storage layers comp |
| 7599228 |
Flash memory device having increased over-erase correction efficiency and robustness against dev |
October 6, 2009 |
| A memory device is provided including circuitry for correcting an over-erased memory cell in the memory device. The memory device may include a substrate. A control gate and a floating gate may be formed over the substrate. The memory device may include a source region and a drain re |
| 7589371 |
Semiconductor device and fabrication method therefor |
September 15, 2009 |
| The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches (11) formed in a semiconductor substrate (10), first ONO films (18) provided on both side surfaces of the trenches, and first word lines (22) provided on side |
| 7582893 |
Semiconductor memory device comprising one or more injecting bilayer electrodes |
September 1, 2009 |
| The subject invention provides systems and methods that facilitate formation of semiconductor memory devices comprising memory cells with one or more injecting bilayer electrodes. Memory arrays generally comprise bit cells that have two discrete components; a memory element and a sel |
| 7579631 |
Variable breakdown characteristic diode |
August 25, 2009 |
| A memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes is disclosed. The controllably conductive media includes a passive layer made of super ionic material and an active layer. When an external stimuli, such as an appli |
| 7574576 |
Semiconductor device and method of controlling the same |
August 11, 2009 |
| A semiconductor device includes: a memory cell array that includes non-volatile memory cells; a first memory region and a second memory region that are located in the memory cell array, the first memory region being protected during a protecting period, the second memory region being |
| 7573743 |
Semiconductor device and control method of the same |
August 11, 2009 |
| A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among sector |
| 7573103 |
Back-to-back NPN/PNP protection diodes |
August 11, 2009 |
| A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN diode includes a p-type substrate connected to ground, a well of n-type material formed in the p-type substrate in direct physical contact with the p-type substrate and elec |
| 7573091 |
Semiconductor device and method of manufacturing the same |
August 11, 2009 |
| The present invention relates to a semiconductor device that includes a semiconductor substrate (10) having source/drain diffusion regions (14) formed therein and control gates (20) formed thereon, with grooves (18) being formed on the surface of the semiconductor substrate (10) and bein |
| 7572727 |
Semiconductor formation method that utilizes multiple etch stop layers |
August 11, 2009 |
| The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing |
| 7567457 |
Nonvolatile memory array architecture |
July 28, 2009 |
| An apparatus comprising a two or three dimensional array of a plurality of pairs of non-volatile memory ("NVM") cells coupled to enable program and erase of the NVM cells. The plurality of pairs of NVM cells is electrically connected to word lines and bit lines. Each pair of NVM cell |
| 7567076 |
Automated loading/unloading of devices for burn-in testing |
July 28, 2009 |
| The automatic loading and unloading of devices for burn-in testing is facilitated by loading burn-in boards in a magazine with the stacked boards in the magazine moved into and out of a burn-in oven by means of a trolley. The trolley can include an elevator whereby a plurality of mag |
| 7566978 |
Semiconductor device and programming method |
July 28, 2009 |
| The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion |
| 7566628 |
Process for making a resistive memory cell with separately patterned electrodes |
July 28, 2009 |
| Methods of making MIM structures and the resultant MIM structures are provided. The method involves forming a top electrode layer over a bottom electrode and an insulator on a substrate and forming a top electrode by removing portions of the top electrode layer. The bottom electrode, |
| 7565477 |
Semiconductor device and method of controlling the same |
July 21, 2009 |
| A semiconductor device includes: memory regions that include non-volatile memory cells; disabling information memory units that correspond to the memory regions, each of the disabling information memory units storing first program disabling information indicating whether programming is t |
| 7564720 |
Nonvolatile storage and erase control |
July 21, 2009 |
| A nonvolatile storage including a plurality of blocks each serving as one unit in erasing operation and performs a plurality of erasing operations successively, the nonvolatile storage comprising: a volatile memory cell array for storing erase setting information on each block, the i |
| 7564708 |
Method of programming memory device |
July 21, 2009 |
| In a memory device having first and second electrodes and active and passive layers between the electrodes, or a memory device having first and second electrodes and an insulating layer between and in contact with electrodes, the device may be programmed in the ionic mode by applying |
| 7564091 |
Memory device and methods for its fabrication |
July 21, 2009 |
| A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an |
| 7561484 |
Reference-free sampled sensing |
July 14, 2009 |
| Systems and methods for extending the usable lifetime of memory cells by utilizing reference-free sampled sensing. A stimulus component applies a plurality of different stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cel |
| 7561471 |
Cycling improvement using higher erase bias |
July 14, 2009 |
| Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cell |
| 7561465 |
Methods and systems for recovering data in a nonvolatile memory array |
July 14, 2009 |
| One embodiment of the invention relates to a method for refreshing a nonvolatile memory array. In the method, a threshold voltage of a multi-bit memory cell is analyzed to determine if it has drifted outside of a number of allowable voltage windows, wherein each allowable voltage win |
| 7561457 |
Select transistor using buried bit line from core |
July 14, 2009 |
| A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The select transistors are formed at substantially the same pitch as the memory cells in t |
| 7558907 |
Virtual memory card controller |
July 7, 2009 |
| The claimed subject matter can provide an architecture that can transparently provide more robust interactions between a host device and a smartcard or other mass media storage device by way of block level read or write operations provided as part of a standard interface protocol. A |
| 7558904 |
Controller, data memory system, data rewriting method, and computer program product |
July 7, 2009 |
| The controller of the present invention includes an address management table that stores address information of valid data among the data stored in a flash memory, a status flag stored in the flash memory indicating that the data before rewriting and the data after rewriting are in p |
| 7558123 |
Efficient and systematic measurement flow on drain voltage for different trimming in flash silic |
July 7, 2009 |
| Systems and methods that facilitate characterization of a flash memory device are presented. A characterization component can be associated with a regulator component included in a memory device to facilitate setting and measuring respective drain voltage levels for programming, erase, a |
| 7558116 |
Regulation of boost-strap node ramp rate using capacitance to counter parasitic elements in chan |
July 7, 2009 |
| Systems and/or methods that facilitate accessing data in a memory are presented. The memory can be flash memory that includes a plurality of sectors in an array that can be associated with a decoder component that includes a regulator component, which facilitates performing read oper |
| 7558101 |
Scan sensing method that improves sensing margins |
July 7, 2009 |
| Systems and methods for improving memory cell sensing margins by utilizing an optimal reference stimulus. A stimulus component applies a plurality of different reference stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory ce |
| 7554204 |
Die offset die to die bonding |
June 30, 2009 |
| A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge of |
| 7553727 |
Using implanted poly-1 to improve charging protection in dual-poly process |
June 30, 2009 |
| The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the |
| 7550761 |
Switchable memory diode--a new memory device |
June 23, 2009 |
| Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric se |
| 7538383 |
Two-bit memory cell having conductive charge storage segments and method for fabricating same |
May 26, 2009 |
| According to one exemplary embodiment, a two-bit memory cell includes a gate stack situated over a substrate, where the gate stack includes a charge-trapping layer. The charge-trapping layer includes first and second conductive segments and a nitride segment, where the nitride segmen |
| 7535767 |
Reading multi-cell memory devices utilizing complementary bit information |
May 19, 2009 |
| Providing differentiation between overlapping memory cell bits in multi-cell memory devices is described herein. By way of example, select groups of memory cells of the multi-cell memory devices can be iteratively disabled to render state distributions of remaining, non-disabled memo |
| 7534732 |
Semiconductor devices with copper interconnects and composite silicon nitride capping layers |
May 19, 2009 |
| Cu interconnects are formed with composite capping layers for reduced electromigration, improved adhesion between Cu and the capping layer, and reduced charge loss in associated non-volatile transistors. Embodiments include depositing a first relatively thin silicon nitride layer having |
| 7532518 |
Compensation method to achieve uniform programming speed of flash memory devices |
May 12, 2009 |
| Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance |
| 7525853 |
Semiconductor device and method for boosting word line |
April 28, 2009 |
| A semiconductor device of the present invention includes a booster circuit that boosts a selected word line (WL) to a given voltage higher than a power supply voltage and a charge pump circuit that retains the boosted word line (WL) at the first given voltage. When the booster circuit |
| 7512743 |
Using shared memory with an execute-in-place processor and a co-processor |
March 31, 2009 |
| The claimed subject matter provides systems and/or methods that facilitate sharing of a memory, having a single channel of access, between two or more processors. A host processor can be operatively connected to a co-processor and the memory in series. The host processor can execute in |
| 7507661 |
Method of forming narrowly spaced flash memory contact openings and lithography masks |
March 24, 2009 |
| A method is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device wafer, comprising creating a series of optical features spaced on the lithography mask from one another along a first directio |
