| Patent Number |
Title Of Patent |
Date Issued |
| RE39957 |
Method of making semiconductor package with heat spreader |
December 25, 2007 |
| A method is provided of making a semiconductor package with a heat spreader in which a chip carrier module plate consisting of a plurality of array-arranged chip carriers is mounted with at least one chip on each of the chip carriers. A heat spreader module plate is attached to the c |
| D498760 |
Digital memory card |
November 23, 2004 |
|
| D493799 |
Digital memory card |
August 3, 2004 |
|
| D492314 |
IC card type circuit module |
June 29, 2004 |
|
| 7615862 |
Heat dissipating package structure and method for fabricating the same |
November 10, 2009 |
| A heat dissipating package structure includes a chip carrier; a semiconductor chip mounted and electrically connected to the chip carrier; a heat spreader having a first surface, an opposed second surface and a hollow structure, the second surface of the heat spreader being mounted o |
| 7608915 |
Heat dissipation semiconductor package |
October 27, 2009 |
| A heat dissipation semiconductor package includes a chip carrier, a semiconductor chip, a heat conductive adhesive, a heat dissipation member, and an encapsulant. The semiconductor chip is flip-chip mounted on the chip carrier and defined with a heat conductive adhesive mounting area |
| 7573722 |
Electronic carrier board applicable to surface mounted technology (SMT) |
August 11, 2009 |
| An electronic carrier board is provided, including a carrier, at least two paired bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings corresponding in position to the two bond pads. The openings are aligned in the sam |
| 7564140 |
Semiconductor package and substrate structure thereof |
July 21, 2009 |
| A semiconductor package and a substrate structure thereof are provided. A solder mask layer applied on the substrate structure is formed with outwardly extended openings corresponding to corner portions of a chip mounting area of the substrate structure. When a flip-chip semiconductor |
| 7459770 |
Lead frame structure having blocking surfaces and semiconductor package integrated with the lead |
December 2, 2008 |
| A lead frame structure is provided, which includes a die pad having a first mounting portion and a second mounting portion separated from the first mounting portion by a gap. The first and second mounting portions are formed with corresponding blocking surfaces bordering the gap, so as |
| 7410836 |
Method for fabricating a photosensitive semiconductor package |
August 12, 2008 |
| A photosensitive semiconductor package, a method for fabricating the same, and a lead frame thereof are proposed. The lead frame has a die pad and a plurality of leads, wherein at least one recessed portion is formed at an end of each lead close to the die pad, and at least one recessed |
| 7410835 |
Method for fabricating semiconductor package with short-prevented lead frame |
August 12, 2008 |
| A short-prevented lead frame and a method for fabricating a semiconductor package with the lead frame are proposed, wherein each lead of the lead frame is formed with a thickness-reduced portion at a peripheral position of the lead frame, allowing thickness-reduced portions of adjacent l |
| 7365364 |
Sensor semiconductor device with sensor chip |
April 29, 2008 |
| A sensor semiconductor device and a method for fabricating the same are proposed. A sensor chip is mounted on a substrate, and a dielectric layer and a circuit layer are formed on the substrate, wherein the circuit layer is electrically connected to the substrate and the sensor chip. The |
| 7358177 |
Fabrication method of under bump metallurgy structure |
April 15, 2008 |
| A fabrication method of under bump metallurgy (UBM) structure is provided. A blocking layer is applied over a surface of a semiconductor element formed with at least one bond pad and a passivation layer thereon. The passivation layer covers the semiconductor element and exposes the bond |
| 7339199 |
Semiconductor package including light emitter and IC |
March 4, 2008 |
| The is to disclose a semiconductor package featuring inclusion of light emitter(s) providing light to indicate the states of the semiconductor package as a whole and/or the chip(s) therein. The light emitter is in an original state or flashing state or emitting state according to the |
| 7271024 |
Method for fabricating sensor semiconductor device |
September 18, 2007 |
| A sensor semiconductor device and a method for fabricating the same are proposed. A plurality of metal bumps and a sensor chip are mounted on a substrate. A dielectric layer and a circuit layer are formed on the substrate, wherein the circuit layer is electrically connected to the me |
| 7205485 |
Printed circuit board and method for fabricating the same |
April 17, 2007 |
| A printed circuit board and a method for fabricating the same is provided. A substrate having a core layer and a plurality of pairs of bond pads thereon is prepared with at least one opening formed on the core layer between each pair of the bond pads. A solder mask layer covers the core |
| 7141868 |
Flash preventing substrate and method for fabricating the same |
November 28, 2006 |
| A flash preventing substrate and a method for fabricating the same are proposed. A core defined with a plurality of substrate units is prepared. A circuit patterning process is performed to form circuit structures on the core corresponding to the substrate units, plating buses between th |
| 7129119 |
Method for fabricating semiconductor packages |
October 31, 2006 |
| A method for fabricating semiconductor packages is proposed. A plurality of substrates are prepared each having a chip thereon. Length and width of each substrate are equal to predetermined length and width of the semiconductor package. A carrier having a plurality of openings is pre |
| 6963135 |
Semiconductor package for memory chips |
November 8, 2005 |
| A semiconductor package includes two substrates each having a plurality of electrical connection pads, at least one chip mounted on each of the substrates, an encapsulation body formed on each of the substrates for encapsulating the chip, and an cover for receiving the substrates and the |
| 6919627 |
Multichip module |
July 19, 2005 |
| A multi-chip module is proposed, which is designed to pack two or more semi-conductor chips in a stacked manner over a chip carrier in a single package. The multi-chip module is characterized by the use of adhesive with fillers to allow the topmost chip (i.e. the second chip) superimpose |
| 6830957 |
Method of fabricating BGA packages |
December 14, 2004 |
| A method of fabricating BGA (Ball Grid Array) packages is proposed, which utilizes a specially-designed carrier to serve as an auxiliary tool to package semiconductor chips on substrates. The carrier is formed with a plurality of cavities respective for receiving a substrate and in c |
| 6798054 |
Method of packaging multi chip module |
September 28, 2004 |
| A method of packaging a multi chip module (MCM) with low cost and high reliability is disclosed. In the MCM process, a plurality of bare chips and CPSs, such as CPU or memory device, are integrated on a substrate to increase the package density. The method discards the high cost KGD |
| 6787921 |
Array structure of solder balls able to control collapse |
September 7, 2004 |
| A solder ball array type package structure is able to control collapse. The package includes a substrate, a carrier, a plurality of dies, a molding compound and a plurality of solder balls. The substrate has at least one active surface. Pads are located on the first surface of the substr |
| 6787918 |
Substrate structure of flip chip package |
September 7, 2004 |
| A substrate structure of Flip Chip package includes a plurality of patterned circuit layers alternately stacking up with at least an insulative layer for isolating the patterned circuit layers. The patterned circuit layers are electrically connected each other wherein one of the patt |
| 6781245 |
Array structure of solder balls able to control collapse |
August 24, 2004 |
| A solder ball array type package structure is able to control collapse. The package includes a substrate, a carrier, a plurality of dies, a molding compound and a plurality of solder balls. The substrate has at least one active surface. Pads are located on the first surface of the substr |
| 6781222 |
Semiconductor package having vertically mounted passive devices under a chip and a fabricating m |
August 24, 2004 |
| A semiconductor package and its fabricating method are proposed, in which a plurality of passive devices are integrated under a semiconductor chip, so as to increase the layout number of the passive devices in the semiconductor package and enhance the flexibility of substrate routabi |
| 6777266 |
Dual-chip integrated circuit package and method of manufacturing the same |
August 17, 2004 |
| A dual-chip integrated circuit package and a method for manufacturing such a dual-chip integrated circuit package are proposed, which can help prevent the occurrence of cracking and delamination in the chips and the occurrence of voids in the encapsulant during the manufacture process. T |
| 6772512 |
Method of fabricating a flip-chip ball-grid-array package without causing mold flash |
August 10, 2004 |
| A method of fabricating a FCBGA (Flip-Chip Ball-Grid-Array) package without causing mold flash is proposed, which is characterized by the forming of a dummy pad over the back surface of the substrate to allow the portion of the solder mask formed over a vent hole in the substrate to be |
| 6767753 |
Image sensor of a quad flat package |
July 27, 2004 |
| An image sensor of a quad flat non-leaded package (QFN). The image sensor of a quad flat non-leaded package includes a lead frame having a plurality of leads and a die pad, and the leads are located around a periphery of the die pad. A molding structure is formed around an outer boundary |
| 6713864 |
Semiconductor package for enhancing heat dissipation |
March 30, 2004 |
| The present invention discloses a semiconductor package for enhancing heat dissipation. Only the structures of the semiconductor package that conventionally located in one of the two parts of the mold conventionally used to encapsulate a semiconductor package are encapsulated. A heat sin |
| 6713321 |
Super low profile package with high efficiency of heat dissipation |
March 30, 2004 |
| A super low profile package with high efficiency of heat dissipation comprises the substrate, the heat sink, the die, the wires and the plastic mold. The heat sink adheres to the ground ring by the extending part of the heat sink, and the first surface of the die adheres to the heat sink |
| 6696749 |
Package structure having tapering support bars and leads |
February 24, 2004 |
| A package structure having tapering support bars and leads. The package structure has at least a lead frame, a die, a plurality of conductive wires and an encapsulating plastic body. The lead frame has a first surface and has at least a package unit. The package unit has a die pad, a |
| 6670219 |
Method of fabricating a CDBGA package |
December 30, 2003 |
| A CDBGA package comprises a thermal dissipating substrate and a plurality of conductive bumps. A plurality of vias are formed on a circuit substrate and correspond to the conductive bumps. A plurality of ground pads, ball pads and nodes are formed on the circuit substrate, wherein the gr |
| 6653728 |
Tray for ball grid array semiconductor packages |
November 25, 2003 |
| A tray for ball grid array (BGA) semiconductor packages is provided, composed of a body, protruding portions and positioning portions. The body is formed with a plurality of recessed cavities, and the protruding portions are formed in the recessed cavities corresponding to area free of |
| 6650015 |
Cavity-down ball grid array package with semiconductor chip solder ball |
November 18, 2003 |
| A cavity-down ball grid array package includes a substrate having a through cavity provided therein. A heat sink is attached to the substrate and a semiconductor chip in the cavity is attached to the heat sink and electrically connected to the substrate. A ball grid array is on the s |
| 6650009 |
Structure of a multi chip module having stacked chips |
November 18, 2003 |
| A structure of a multi chip module package having stacked chips, having at least a substrate, a main chip, a plurality of chip sets, a plurality of spacers, a plurality of glue layers, a plurality of wires, and a mold compound. The substrate has a front surface and a back surface opposit |
| 6642735 |
Semiconductor package for chip with testing contact pad connected to outside |
November 4, 2003 |
| A semiconductor package for chip with testing contact pad includes a chip, a plurality of leads, at least a flow-conducting plate, and a molding compound. The chip has an active surface provided with a plurality of functional contact pads and at least a testing contact pad. The leads are |
| 6603196 |
Leadframe-based semiconductor package for multi-media card |
August 5, 2003 |
| A leadframe-based semiconductor package is proposed for the packaging of a semiconductor device, such as a multi-media card (MMC) chipset. The proposed semiconductor package is characterized by the use of a leadframe, rather than BT substrate or film, as the chip carrier for MMC chipset. |
| 6593662 |
Stacked-die package structure |
July 15, 2003 |
| A stacked-die package structure comprises a carrier, dies, spacers, adhesive layers, conductive lines, a mold compound, and solder balls. The carrier has an upper surface and a back surface opposite to the upper surface. The dies substantially having the same sizes are stacked one by |
| 6583499 |
Quad flat non-leaded package and leadframe for use in a quad flat non-leaded package |
June 24, 2003 |
| A quad flat non-leaded package comprises: a die pad having a first upper surface and a corresponding first lower surface thereon a plurality of interlacing slots are formed, each of the interlacing slots extending to the edges of the die pad to form a plurality of island-like blocks; a |
| 6573610 |
Substrate of semiconductor package for flip chip package |
June 3, 2003 |
| A semiconductor package structure for Flip Chip package includes at least an insulative core layer and a plurality of patterned circuit layers alternately stacking up each other. The patterned circuit layers are electrically connected each other wherein one of the patterned circuit l |
| 6559525 |
Semiconductor package having heat sink at the outer surface |
May 6, 2003 |
| A semiconductor package having heat sink at the outer surface is constructed on a lead frame. The package comprises a chip, a die pad, a plurality of leads, a plurality of bonding wires, and a molding compound. The die pad has a first surface and a second surface, and the chip has its |
| 6555902 |
Multiple stacked-chip packaging structure |
April 29, 2003 |
| A packaging structure comprises a substrate, a plurality of semiconductor chips contiguously mounted into a plurality of stacked semiconductor chip sets, a plurality of supporting members, a plurality of adhesive layers, a plurality of wires and a molding compound. Each of the semiconduc |
| 6555296 |
Fine pitch wafer bumping process |
April 29, 2003 |
| A fine pitch wafer bumping process comprises: providing a wafer that has a plurality of contact pads exposed by a passivation layer formed on the surface of the wafer, wherein an under bump metal (UBM) is formed respectively on each contact pad; on the surface of the wafer, forming a |
| 6548911 |
Multimedia chip package |
April 15, 2003 |
| A substrate unit has a first surface and a corresponding second surface, and a plurality of nodes and at least a die pad are formed on the first surface of the substrate unit. A plurality of external nodes is formed on the second surface of the substrate unit, and the external nodes are |
| 6545332 |
Image sensor of a quad flat package |
April 8, 2003 |
| An image sensor of a quad flat non-leaded package (QFN). The image sensor of a quad flat non-leaded package includes a lead frame having a plurality of leads and a die pad, and the leads are located around a periphery of the die pad. A molding structure is formed around an outer boundary |
| 6543128 |
Ball grid array package and its fabricating process |
April 8, 2003 |
| A ball grid array package comprises a substrate having a first surface and a second surface, a chip, an insulating material, and a solder ball. The surface of the substrate comprises ball pads, conducting traces, and solder masks wherein the conducting traces are disposed in between the |
| 6541854 |
Super low profile package with high efficiency of heat dissipation |
April 1, 2003 |
| A super low profile package with high efficiency of heat dissipation comprises the substrate, the heat sink, the die, the wires and the plastic mold. The heat sink adheres to the ground ring by the extending part of the heat sink, and the first surface of the die adheres to the heat sink |
| 6541307 |
Multimedia chip package |
April 1, 2003 |
| A substrate unit has a first surface and a corresponding second surface, and a plurality of nodes and at least a die pad are formed on the first surface of the substrate unit. A plurality of external nodes is formed on the second surface of the substrate unit, and the external nodes are |
| 6531762 |
Semiconductor package |
March 11, 2003 |
| A semiconductor package is proposed, in which a substrate is formed with a chip bonding area and a plurality of bond fingers surrounding the chip bonding area, and a plurality of bridging elements are disposed in a stagger manner between the chip bonding area and the bond fingers on the |
