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Siliconix incorporated Patents
Assignee:
Siliconix incorporated
Address:
Santa Clara, CA
No. of patents:
238
Patents:


1 2 3 4 5










Patent Number Title Of Patent Date Issued
D472528 Semiconductor chip package April 1, 2003
D466873 Semiconductor chip package December 10, 2002
7795675 Termination for trench MIS device September 14, 2010
A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is
7704836 Method of fabricating super trench MOSFET including buried source electrode April 27, 2010
In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an "off" condition, the bias of the buried source el
7557409 Super trench MOSFET including buried source electrode July 7, 2009
In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an "off" condition, the bias of the buried source el
7435650 Process for manufacturing trench MIS device having implanted drain-drift region and thick bottom October 14, 2008
A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the N-epi
7416947 Method of fabricating trench MIS device with thick oxide layer in bottom of trench August 26, 2008
A trench MIS device includes a thick dielectric layer at the bottom of the trench. The thick dielectric layer can be formed by the deposition or thermal growth of a dielectric material, such as silicon dioxide, on the bottom portion of the trench. The thick dielectric layer, which reduce
7394150 Semiconductor package including die interposed between cup-shaped lead frame and lead frame havi July 1, 2008
A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of
7326995 Trench MIS device having implanted drain-drift region and thick bottom oxide February 5, 2008
A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. The thick insulating
7291884 Trench MIS device having implanted drain-drift region and thick bottom oxide November 6, 2007
A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the N-epi
7268032 Termination for trench MIS device having implanted drain-drift region September 11, 2007
A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is
7238551 Method of fabricating semiconductor package including die interposed between cup-shaped lead fra July 3, 2007
A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of
7233043 Triple-diffused trench MOSFET June 19, 2007
A trench-gated MOSFET includes adjacent mesas formed on opposite sides of a trench. A body region in the first mesa extends downward below the level of the trenches and laterally across the bottom of the trenches. The body region in the second mesa extends part of the way down the mesa,
7186609 Method of fabricating trench junction barrier rectifier March 6, 2007
A Schottky rectifier includes a rectifying interface between a semiconductor body and a metal layer. Trenches are formed in the surface of the semiconductor body and regions of a conductivity type opposite to the conductivity type of the body are formed along the sidewalls and bottom
7183610 Super trench MOSFET including buried source electrode and method of fabricating the same February 27, 2007
In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an "off" condition, the bias of the buried source el
7118953 Process of fabricating termination region for trench MIS device October 10, 2006
A trench MIS device is formed in a semiconductor die that contains a P-epitaxial layer that overlies an N+ substrate and an N-epitaxial layer. In one embodiment, the device includes a drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. A termination
7045857 Termination for trench MIS device having implanted drain-drift region May 16, 2006
A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is
7033876 Trench MIS device having implanted drain-drift region and thick bottom oxide and process for man April 25, 2006
A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. The thick insulating
7012005 Self-aligned differential oxidation in trenches by ion implantation March 14, 2006
In accordance with the present invention, a trench MOSFET is formed by creating a trench in a semiconductor substrate. A portion of either a side wall of the trench or the bottom of the trench is implanted with an implant species. An insulating layer is then grown overlying the bottom
7009247 Trench MIS device with thick oxide layer in bottom of gate contact trench March 7, 2006
A trench MIS device includes a thick dielectric layer at the bottom of the trench. The thick dielectric layer can be formed by the deposition or thermal growth of a dielectric material, such as silicon dioxide, on the bottom portion of the trench. The thick dielectric layer, which reduce
6927451 Termination for trench MIS device having implanted drain-drift region August 9, 2005
A trench MIS device is formed in a semiconductor die that contains a P-epitaxial layer that overlies an N+ substrate and an N-epitaxial layer. In one embodiment, the device includes a drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. A termination
6921697 Method for making trench MIS device with reduced gate-to-drain capacitance July 26, 2005
Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the
6913977 Triple-diffused trench MOSFET and method of fabricating the same July 5, 2005
A trench-gated MOSFET includes adjacent mesas formed on opposite sides of a trench. A body region in the first mesa extends downward below the level of the trenches and laterally across the bottom of the trenches. The body region in the second mesa extends part of the way down the mesa,
6909170 Semiconductor assembly with package using cup-shaped lead-frame June 21, 2005
A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side
6903412 Trench MIS device with graduated gate oxide layer June 7, 2005
The gate oxide layer of a trench MIS device includes a graduated transition region, where the thickness of the gate oxide layer decreases gradually from a thick section adjacent the bottom of the trench to a thin section adjacent the sidewall of the trench. The PN junction between the bo
6882000 Trench MIS device with reduced gate-to-drain capacitance April 19, 2005
Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the
6875657 Method of fabricating trench MIS device with graduated gate oxide layer April 5, 2005
A process for manufacturing a trench MIS device includes depositing a conformal nitride layer in the trench; etching the nitride layer to create an exposed area at the bottom of the trench; and heating the substrate and thereby growing an oxide layer in the exposed area. This process cau
6849898 Trench MIS device with active trench corners and thick bottom oxide February 1, 2005
Trench MOSFETs including active corner regions and a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such MOSFETs. In an exemplary embodiment, the trench MOSFET includes a thick insulative layer centrally located at the bottom of the
6838722 Structures of and methods of fabricating trench-gated MIS devices January 4, 2005
In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal
6764906 Method for making trench mosfet having implanted drain-drift region July 20, 2004
A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. A trench is formed in the epitaxial layer. A deep implanted N layer is formed below the trench at the interface between the substrate and the epitaxial layer, and N-type dopant
6744124 Semiconductor die package including cup-shaped leadframe June 1, 2004
A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side
6709930 Thicker oxide formation at the trench bottom by selective oxide deposition March 23, 2004
A trench MOSFET is formed by creating a trench in a semiconductor substrate, then forming a barrier layer over a portion of the side wall of the trench. A thick insulating layer is deposited in the bottom of the trench. The barrier layer is selected such that the thick insulating layer
6627950 Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry September 30, 2003
Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned, using a shaped deep body junction that partly lies below the trench bottom, and using special procedures for growth of ga
6600193 Trench MOSFET having implanted drain-drift region July 29, 2003
A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. An N-type dopant is implanted through the bottom of the trench into the P-epitaxial layer to form a buried layer below the trench, and after a up-diffusion step a N drain-drift reg
6590440 Low-side bidirectional battery disconnect switch July 8, 2003
A bidirectional battery disconnect switch, i.e., a switch which is capable of blocking a voltage in either direction when open and conducting a current in either direction when closed, is disclosed. The switch includes a four-terminal MOSFET having no source/body short and circuitry for
6534366 Method of fabricating trench-gated power MOSFET March 18, 2003
A trench-gated power MOSFET contains a highly doped region in the body region which forms a PN junction diode with the drain at the center of the MOSFET cell. This diode has an avalanche breakdown voltage which is lower than the breakdown voltage of the drain-body junction near to the wa
6509233 Method of making trench-gated MOSFET having cesium gate oxide layer January 21, 2003
Cesium is implanted into the gate oxide layer of a vertical trench-gated MOSFET. The cesium, which is an electropositive material, reduces the threshold voltage of the device and lowers the on-resistance by improving the accumulation region adjacent the bottom of the trench.
6476442 Pseudo-Schottky diode November 5, 2002
An N-channel MOSFET is fabricated with its source, body and gate connected together and biased at a positive voltage with respect to its drain. The resulting two-terminal device functions generally in the manner of a diode but has a significantly lower turn-on voltage than a conventional
6444527 Method of operation of punch-through field effect transistor September 3, 2002
A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source
6392290 Vertical structure for semiconductor wafer-level chip scale packages May 21, 2002
In a semiconductor package for a chip having terminals on both sides, for example, a power MOSFET in which the gate and source terminals are on the front side and the drain terminal is on the back side, electrical contact is made with the back side terminal by extending vias, which can t
6348712 High density trench-gated power MOSFET February 19, 2002
A trench-gated power MOSFET contains a highly doped region in the body region which forms a PN junction diode with the drain at the center of the MOSFET cell. This diode has an avalanche breakdown voltage which is lower than the breakdown voltage of the drain-body junction near to the wa
6300744 High-efficiency battery charger October 9, 2001
Where an AC adapter is used to supply power to both an electronic device such as a notebook computer and a rechargeable battery, as where the computer is turned on while the battery is being recharged, the voltage at the output terminal of the AC adapter is detected and delivered to
6285060 Barrier accumulation-mode MOSFET September 4, 2001
In a trench-gated MOSFET, a lightly doped drift region of the N-type drain lies in the mesa between the trenches. The gate is doped with N-type material so that depletion regions are formed in the drift region when the gate voltage is equal to zero. The depletion regions merge at the cen
6277695 Method of forming vertical planar DMOSFET with self-aligned contact August 21, 2001
The metal contact to the source and body regions in a vertical planar DMOSFET is formed by fabricating a sidewall spacer on the gate of the MOSFET. With the metal contact self-aligned to the gate in this way, the lateral dimension of each of the cells in the DMOSFET can be significantly
6249041 IC chip package with directly connected leads June 19, 2001
An improved semiconductor device is disclosed. In one embodiment, the semiconductor device includes a semiconductor chip with contact areas on the top or bottom surface. A first lead assembly, formed from a semi-rigid sheet of conductive material, has a lead assembly contact attached to
6239463 Low resistance power MOSFET or other device containing silicon-germanium layer May 29, 2001
A power MOSFET or other semiconductor device contains a layer of silicon combined with germanium to reduce the on-resistance of the device. The proportion of germanium in the layer is typically in the range of 1-40%. To achieve desired characteristics the concentration of germanium in th
6204533 Vertical trench-gated power MOSFET having stripe geometry and high cell density March 20, 2001
A vertical trench-gated power MOSFET includes MOSFET cells in the shape of longitudinal stripes. The body diffusion of each cell contains a relatively heavily-doped region which extends parallel to the length of the cell and contacts an overlying metal source/body contact layer at sp
6172383 Power MOSFET having voltage-clamped gate January 9, 2001
A MOSFET contains a voltage clamp including one or more diodes which connects its gate and source. The voltage clamp is designed to break down at a predetermined voltage and thereby protect the gate oxide layer from damage as a result of an excessive source-to-gate voltage. The voltage
6159841 Method of fabricating lateral power MOSFET having metal strap layer to reduce distributed resist December 12, 2000
To reduce the distributed resistance in an integrated circuit die, a relatively thick metal strap layer is deposited on a bus or other conductive path in the top metal layer. The metal strap layer is formed by etching a longitudinal channel in the passivation layer over the bus and p
6140678 Trench-gated power MOSFET with protective diode October 31, 2000
A power MOSFET includes a trenched gate which defines a plurality of MOSFET cells. A protective diffusion is created, preferably in an inactive cell, so as to form a diode that is connected in parallel with the channel region in each of the MOSFET cells. The protective diffusion, which
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