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Silicon Graphics, Inc. Patents
Assignee:
Silicon Graphics, Inc.
Address:
Mountain View, CA
No. of patents:
688
Patents:


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Patent Number Title Of Patent Date Issued
RE38134 System for communications where first priority data transfer is not disturbed by second priority June 3, 2003
The present invention comprises a method and system for implementing prioritized communications in a computer system. The present invention is implemented on a computer system having a microprocessor and a plurality of peripheral devices coupled to the computer system. The system of the
D473561 Set of multi-device faceplates April 22, 2003
D464973 Panel October 29, 2002
D464056 Server product faceplate October 8, 2002
D464054 Panel October 8, 2002
D463796 Industrial rack October 1, 2002
D445112 Server door July 17, 2001
D444474 Drive sled cover July 3, 2001
D444471 Drive sled handle July 3, 2001
D444461 Server cover July 3, 2001
D436950 Radial computer system January 30, 2001
D431242 Computer housing September 26, 2000
D429248 Bezel for a computer August 8, 2000
D419465 Color calibration device for a display January 25, 2000
D419141 Display assembly January 18, 2000
D417203 Computer housing November 30, 1999
D396698 Compact computer housing August 4, 1998
D395286 Compact computer housing June 16, 1998
D393449 Housing for a computer April 14, 1998
D393249 Housing for deskside computer April 7, 1998
D373760 Computer mouse September 17, 1996
D367269 Top front and side portions of a combined computer housing and support stands February 20, 1996
D365585 Video camera used with personal computer December 26, 1995
D363703 Top, sides and front portions of a computer housing October 31, 1995
D341574 Computer housing November 23, 1993
D337323 Electromagnetic shield for attachment to computers July 13, 1993
7603573 System and method for optimizing computational density October 13, 2009
A system and method of designing a computer system having a plurality of processors. A computational density is selected for the computer system, wherein the computational density is expressed as a function of a desired computational power for a given volume. A number of processors is
7593968 Recovery and relocation of a distributed name service in a cluster filesystem September 22, 2009
A cluster of computer system nodes share direct read/write access to storage devices via a storage area network using a cluster filesystem. During relocation of a server for a distributed name service and recovery of a cluster, entries related to the distributed name service for file
7533208 Hot plug control apparatus and method May 12, 2009
An apparatus for controlling a hot plug bus slot on a bus has an input for receiving a set of float signals (i.e., the set may have one or more float signals), and a driver having an output electrically couplable with the bus. The apparatus also has float logic operatively coupled with t
7526125 Method of and apparatus for compressing and uncompressing image data April 28, 2009
The present invention provides for a method of and apparatus for compressing and uncompressing image data. According to one embodiment of the present invention, the method of compressing a color cell comprises the steps of: defining at least four luminance levels of the color cell; g
7518615 Display system having floating point rasterization and floating point framebuffering April 14, 2009
A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten
7500068 Method and system for managing memory in a multiprocessor system March 3, 2009
A method and system for managing memory in a multiprocessor system includes defining the plurality of processor coherence domains within a system coherence domain of the multiprocessor system. The processor coherence domains each include a plurality of processors and a processor memo
7499044 System for synchronizing display of images in a multi-display computer system March 3, 2009
An image display system synchronizes the display of images on a plurality of display devices. The system includes a first computer system generating a first signal representing first image data to be displayed on a first display device, a second computer system generating a second si
7485003 Electromagnetic interference cable backshell assembly for high-density interconnect February 3, 2009
A cable connector assembly for high frequency applications having reduced electromagnetic emissions. Aspects include providing physical spacing and electrical isolation between the signal conductors and a conductive housing. An isolative member provides reduced capacitive coupling. One
7478285 Generation and use of system level defect tables for main memory January 13, 2009
Methods and apparatus for maintaining and utilizing system memory defect tables that store information identifying defective memory locations in memory modules. For some embodiments, the defect tables may be utilized to identify and re-map defective memory locations to non-defective
7466561 System for insertion and extraction of an electronic module December 16, 2008
The system includes a chassis and a printed circuit board (e.g., a motherboard) that is attached to the chassis. The system further includes an actuator that is slidably engaged with the chassis and a cam plate that is rotatably engaged with the chassis. The actuator engages the cam
7464115 Node synchronization for multi-processor computer systems December 9, 2008
A method and apparatus for controlling access by a set of accessing nodes to memory of a home node (in a multimode computer system) determines that each node in the set of nodes has accessed the memory, and forwards a completion message to each node in the set of nodes after it is de
7460126 Scalable method and system for streaming high-resolution media December 2, 2008
A system and method for distributing data (e.g., imaging data such as pixels, or 3D graphics data such as points, lines, or polygons) from a single or a small number of data sources to a plurality of graphical processing units (graphics processors) for processing and display is prese
7453878 System and method for ordering of data transferred over multiple channels November 18, 2008
A multiple channel data transfer system (10) includes a source (12) that generates data packets with sequence numbers for transfer over multiple request channels (14). Data packets are transferred over the multiple request channels (14) through a network (16) to a destination (18). The
7451278 Global pointers for scalable parallel applications November 11, 2008
Mapping of cacheable memory pages from other processes in a parallel job provides a very efficient mechanism for inter-process communication. A trivial address computation can then be used to look up a virtual address that allows the use of cacheable loads and stores to directly access o
7447794 System and method for conveying information November 4, 2008
A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method al
7433441 System and method for adaptively deskewing parallel data signals relative to a clock October 7, 2008
A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to
7425117 System and method for reducing back flow September 16, 2008
A system and method of reducing back flow in an air mover having one or more blades is described. A flap is attached to a blade of the air mover such that, when back flow occurs, the flap obscures all or a portion of the space between blades during back flow.
7406587 Method and system for renaming registers in a microprocessor July 29, 2008
A processor includes an active list to buffer instructions and their associated condition codes for processing. A mapping table in the processor maps a logical register associated with the instruction to a selected one of a plurality of unique physical registers. The selected unique
7406554 Queue circuit and method for memory arbitration employing same July 29, 2008
A memory access arbitration scheme is provided where transactions to a shared memory are stored in an arbitration queue. A collapsible queuing structure and method are provided, such that once a transaction is serviced, higher order entries ripple down in the queue to make room for n
7406086 Multiprocessor node controller circuit and method July 29, 2008
Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/outpu
7405742 Compact flat panel color calibration system July 29, 2008
A compact flat panel color calibration system includes a lens prism optic able to pass a narrow, perpendicular, and uniform cone angle of incoming light to a spectrally non-selective photodetector. The calibration system also includes a microprocessor operable to determine the luminance
7405734 Method and system for presenting three-dimensional computer graphics images using multiple graph July 29, 2008
The present invention provides a method and system for presenting three-dimensional computer graphics images using multiple graphics processing units. The dimensions of the scene to be rendered are bounded by a rectangular volume decomposed into rectangular subvolumes. Vertices of gr
7401116 System and method for allowing remote users to specify graphics application parameters for gener July 15, 2008
A visual server system (10) includes a server (12) having a graphics application (20). The graphics application (20) generates image content and position information. The server (12) streams the image content and the position information for transport over a network link. A plurality
7398359 System and method for performing memory operations in a computing system July 8, 2008
A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In
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