| Patent Number |
Title Of Patent |
Date Issued |
| 7625796 |
Semiconductor device with amorphous silicon MONOS memory cell structure and method for manufactu |
December 1, 2009 |
| A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a |
| 7619435 |
Method and system for derivation of breakdown voltage for MOS integrated circuit devices |
November 17, 2009 |
| A method and system for multi-point (e.g., double-point) GOI test that can efficiently judge failure modes by testing only two points. We can measure leakage currents at only two voltages, which are the cut points of mode A-B and B-C, instead of the whole ramped voltages to save time |
| 7615475 |
Method for fabricating landing polysilicon contact structures for semiconductor devices |
November 10, 2009 |
| A method for forming an integrated circuit device, e.g., memory, logic. The method includes providing a semiconductor substrate (e.g., silicon wafer) comprising a surface region and forming a polysilicon layer overlying the surface region. Preferably, the polysilicon layer is doped w |
| 7612980 |
Method and structure for electrostatic discharge protection of photomasks |
November 3, 2009 |
| A mask for manufacturing integrated circuits and use of the mask. The mask has a mask substrate. The mask also has an active mask region within a first portion of the mask substrate. The active region is adapted to accumulate a pre-determined level of static electricity. The mask also |
| 7611945 |
Method and resulting structure for fabricating DRAM capacitor structure |
November 3, 2009 |
| A method for forming a capacitor structure for a dynamic random access memory device. The method includes forming a device layer overlying a semiconductor substrate, e.g., silicon wafer. The method includes forming a first interlayer dielectric overlying the device layer and forming a |
| 7605470 |
Dummy patterns and method of manufacture for mechanical strength of low K dielectric materials i |
October 20, 2009 |
| A method for fabricating a semiconductor device. The method includes providing a semiconductor substrate including a surface region. The method forms a first interlayer dielectric overlying the surface region and forms an interconnect layer overlying the first interlayer dielectric l |
| 7598179 |
Techniques for removal of photolithographic films |
October 6, 2009 |
| Techniques for removal of photolithographic films used in the manufacture of semiconductor devices are provided. A substrate support member of a first processing chamber includes at least three retractable pins capable of elevating a wafer from a surface of the substrate support member. |
| 7595205 |
Using reverse arrangement for trend test in statistical process control for manufacture of semic |
September 29, 2009 |
| A method for manufacturing semiconductor devices or other types of devices and/or entities. The method includes providing a process (e.g., etching, deposition, implantation) associated with a manufacture of a semiconductor device/ The method includes collecting a plurality informatio |
| 7591659 |
Method and structure for second spacer formation for strained silicon MOS transistors |
September 22, 2009 |
| A method for forming a CMOS semiconductor wafer. The method includes providing a semiconductor substrate (e.g., silicon wafer) and forming a dielectric layer (e.g., silicon dioxide, silicon oxynitride) overlying the semiconductor substrate. The method includes forming a gate layer ov |
| 7582522 |
Method and device for CMOS image sensing with separate source formation |
September 1, 2009 |
| A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer on the substrate, and depositing a first gate region and a second gate region on the gate oxide layer. The first gate region is associated with the |
| 7582517 |
Method for making split dual gate field effect transistor |
September 1, 2009 |
| A method for making a semiconductor device with at least two gate regions. The method includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first plurality of ions into the |
| 7579271 |
Method for forming low dielectric constant fluorine-doped layers |
August 25, 2009 |
| A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing |
| 7573285 |
Multiple point gate oxide integrity test method and system for the manufacture of semiconductor |
August 11, 2009 |
| A method for testing a semiconductor wafer using an in-line process control, e.g., within one or more manufacturing processes in a wafer fabrication facility and/or test/sort operation. The method includes transferring a semiconductor wafer to a test station. The method includes appl |
| 7569487 |
Method for atomic layer deposition of materials using a pre-treatment for semiconductor devices |
August 4, 2009 |
| A method for forming atomic layer deposition. The method includes placing a semiconductor substrate (e.g., wafer, LCD panel) including an upper surface in a chamber. The upper surface includes one or more carbon bearing species and a native oxide layer. The method includes introducing |
| 7557031 |
Etch back with aluminum CMP for LCOS devices |
July 7, 2009 |
| A method for manufacturing an LCOS device includes forming an interlayer dielectric layer overlying a surface region of a substrate. The interlayer dielectric layer is patterned to form a plurality of recessed regions. Each of the recessed regions corresponds to a pixel element for a |
| 7557000 |
Etching method and structure using a hard mask for strained silicon MOS transistors |
July 7, 2009 |
| A method for forming an strained silicon integrated circuit device. The method includes providing a semiconductor substrate and forming a dielectric layer overlying the semiconductor substrate. The method also includes forming a gate layer overlying the dielectric layer and forming a |
| 7554366 |
CMOS driving circuit |
June 30, 2009 |
| A CMOS driving circuit, wherein an output buffer stage with a transistor switch is added to the final buffer stage of a conventional CMOS driving circuit to drive a power transistor. The output buffer stage has two input terminals for DC input voltage, and uses the high voltage of a |
| 7547595 |
Integration scheme method and structure for transistors using strained silicon |
June 16, 2009 |
| A method for forming CMOS integrated circuits. The method forms a blanket layer of silicon dioxide overlying an entirety of the surface region of a first well region and a second well region provided on a semiconductor substrate. The blanket layer of silicon dioxide is overlying the hard |
| 7545201 |
System and method for switching between high voltage and low voltage |
June 9, 2009 |
| A system and method for providing a voltage. The system includes a first transistor including a first gate, a first terminal, and a second terminal. The first terminal is configured to receive a first predetermined voltage, and the first gate is configured to receive a first control |
| 7541827 |
BGA package holder device and method for testing of BGA packages |
June 2, 2009 |
| An apparatus for supporting BGA packages for one or more testing processes is disclosed. The apparatus includes a substrate member. The substrate member has a plurality of contact pads, with each of the contact pads being spatially disposed around a peripheral region of the substrate. Th |
| 7534711 |
System and method for direct etching |
May 19, 2009 |
| System and method for direct etching. According to an embodiment, the present invention provides a method for manufacturing an integrated circuit device. The method includes a step for providing a substrate having a contact region, which is provided between a first word line and a se |
| 7527993 |
Method and structure for fabricating smooth mirrors for liquid crystal on silicon devices |
May 5, 2009 |
| A method for fabricating a liquid crystal on silicon display device. The method includes providing a substrate, e.g., silicon wafer. The method includes forming a transistor layer overlying the substrate. Preferably, the transistor layer has a plurality of MOS devices therein. The method |
| 7521955 |
Method and system for device characterization with array and decoder |
April 21, 2009 |
| A system and method for testing devices. The system includes a plurality of pads and a decoder coupled to a plurality of devices. The decoder is configured to receive a plurality of selection signals from the plurality of pads and select a device from the plurality of devices based on at |
| 7507656 |
Method and structure for low k interlayer dielectric layer |
March 24, 2009 |
| An integrated circuit interconnect structure. The structure includes a substrate and a layer of transistor elements overlying the substrate. A first interlayer dielectric layer is formed overlying the layer of transistor elements. An etch stop layer is formed overlying the first inte |
| 7504269 |
Method for treatment of samples for auger electronic spectrometer (AES) in the manufacture of in |
March 17, 2009 |
| A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at le |
| 7501643 |
Method for controlling charge amount of ion beam and a wafer applied in the method |
March 10, 2009 |
| A method of controlling charge amount of an ion beam, includes providing a semiconductor wafer; forming an insulation layer on the surface of the wafer, with gaps between parts of the insulation layer dividing the surface of the wafer into an open region and a narrow and long region; |
| 7491952 |
Method for controlling charge amount of ion beam and a wafer applied in the method |
February 17, 2009 |
| A method of controlling charge amount of an ion beam includes: providing a semiconductor wafer; forming insulation layer on the surface of the wafer, with gaps between the insulation layer dividing the surface of the wafer into an open region and a narrow and long region; implanting an i |
| 7473595 |
Method for decreasing PN junction leakage current of dynamic random access memory |
January 6, 2009 |
| A method for decreasing a PN junction leakage current of a dynamic random access memory (DRAM), including the steps of: preparing an NMOS transistor formed on a P-type silicon substrate and comprising a drain; forming an insulation oxide layer on the P-type silicon substrate; etching |
| 7468283 |
Method and resulting structure for fabricating test key structures in DRAM structures |
December 23, 2008 |
| A method for fabricating test structures on a wafer for integrated circuits. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of integrated circuit chip structures on the semiconductor substrate and forming a plural |
| 7462556 |
Method of forming low stress multi-layer metallurgical structures and high reliable lead free so |
December 9, 2008 |
| Techniques for manufacturing a bond pad structure are provide. A method includes providing a substrate. A metal pad and passivation layer are formed over the substrate. The passivation layer includes an opening to expose a portion of the metal pad. A first film is deposited at least |
| 7462497 |
Method and system for derivation of breakdown voltage for MOS integrated circuit devices |
December 9, 2008 |
| A method and system for multi-point (e.g., double-point) GOI test that can efficiently judge failure modes by testing only two points. We can measure leakage currents at only two voltages, which are the cut points of mode A-B and B-C, instead of the whole ramped voltages to save time |
| 7456067 |
Method with high gapfill capability for semiconductor devices |
November 25, 2008 |
| A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having |
| 7451553 |
Clean room safety shoe article with removal steel toe housing and method for treating the shoe |
November 18, 2008 |
| A clean room shoe article, e.g., shoe, boot, safety shoe, safety boot. The article has a sole region. The article has an upper particle free polymer material having a toe region and an ankle region. The upper particle free polymer material is coupled to the sole region. The upper particl |
| 7447610 |
Method and system for reliability similarity of semiconductor devices |
November 4, 2008 |
| A method and system for reliability similarity of semiconductor devices. The method includes providing a first plurality of semiconductor devices, providing a second plurality of semiconductor devices, and determining a first reliability associated with the first plurality of semiconduct |
| 7443051 |
System and method for providing adaptive power supply to system on a chip |
October 28, 2008 |
| A system and method for adaptively providing a power supply voltage. The system includes an input/output subsystem configured to receive a first voltage, an analog subsystem configured to receive a second voltage and coupled to the input/output subsystem, a first digital subsystem co |
| 7439538 |
Multi-purpose poly edge test structure |
October 21, 2008 |
| A test structure in accordance with the present invention allows for testing of both V.sub.bd TDDB, and leakage current between adjacent gate features. The test structure comprises a plurality of parallel polysilicon gate structures overlying a substrate. Traces placing alternate gat |
| 7427552 |
Method for fabricating isolation structures for flash memory semiconductor devices |
September 23, 2008 |
| A method for fabricating integrated circuit devices, e.g., Flash memory devices, embedded Flash memory devices. The method includes providing a semiconductor substrate, e.g., silicon, silicon on insulator, epitaxial silicon. In a specific embodiment, the semiconductor substrate has a |
| 7425488 |
Method and structure using a pure silicon dioxide hardmask for gate patterning for strained sili |
September 16, 2008 |
| A partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the |
| 7424700 |
Method and system for selective optical pattern compensation |
September 9, 2008 |
| A method and system for making a photographic mask. The method includes determining a first contact area, processing information associated with the first contact area, and determining whether a first optical compensation should be applied to the first contact area based on at least |
| 7414450 |
System and method for adaptive power supply to reduce power consumption |
August 19, 2008 |
| A system and method for adaptively providing a power supply voltage. The system includes an oscillator configured to receive an output voltage and generate a firs signal. The first signal is associated with a first frequency and a first period. Additionally, the system includes a fre |
| 7403047 |
System and method for power-on control of input/output drivers |
July 22, 2008 |
| A system and method for controlling an input/output driver. The system includes a control system configured to receive a first supply voltage and a second supply voltage and generate a control signal, and a first transistor including a first gate, a first terminal, and a second termi |
| 7396693 |
Multiple point gate oxide integrity test method and system for the manufacture of semiconductor |
July 8, 2008 |
| A method for testing a semiconductor wafer using an in-line process control, e.g., within one or more manufacturing processes in a wafer fabrication facility and/or test/sort operation. The method includes transferring a semiconductor wafer to a test station. The method includes appl |
| 7381636 |
Planar bond pad design and method of making the same |
June 3, 2008 |
| Techniques for an integrated circuit device with planar bond pads are provided. A metal layer region is formed on a substrate. The integrated circuit device also includes a passivation layer that has an opening formed around the metal layer region. The passivation layer and a top sur |
| 7372339 |
Phase lock loop indicator |
May 13, 2008 |
| A phase-locked loop (PLL) circuit includes a power-on-reset (POR) to reset a digital block and set an initial input voltage value VCTRL of voltage-controlled oscillator (VCO). An input divider and a feedback divider are provided to set the frequency ratio of output to input and to ra |
| 7368989 |
High bandwidth apparatus and method for generating differential signals |
May 6, 2008 |
| An apparatus and method for generating differential signals. The apparatus includes a first operational amplifier receiving a first signal, a second operational amplifier receiving a second signal, and a first transistor. The first transistor includes a first gate, a first terminal, and |
| 7353124 |
Device and method for voltage regulator with low standby current |
April 1, 2008 |
| An apparatus and method for providing a reference voltage for regulating voltage levels. The apparatus includes a first voltage generation system configured to receive a first control signal and output a calibration voltage, a voltage adjustment system configured to receive the calib |
| 7352210 |
Device and method for voltage regulator with stable and fast response and low standby current |
April 1, 2008 |
| An apparatus and method for regulating voltage levels. The apparatus includes a first transistor and a second transistor. The first transistor and the second transistor are each coupled to a first current source and a second current source. Additionally, the apparatus includes a third |
| 7345500 |
Method and system for device characterization with array and decoder |
March 18, 2008 |
| A system and method for testing devices. The system includes a plurality of pads and a decoder coupled to a plurality of devices. The decoder is configured to receive a plurality of selection signals from the plurality of pads and select a device from the plurality of devices based on at |
| 7335566 |
Polysilicon gate doping method and structure for strained silicon MOS transistors |
February 26, 2008 |
| A method of fabricating an integrated circuit including strained silicon bearing regions. The method forms a blanket layer of material having an initial thickness overlying a source region, a drain region, and a gate structure of an MOS device to cover an upper surface of the gate st |
| 7335546 |
Method and device for CMOS image sensing with separate source formation |
February 26, 2008 |
| A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer on the substrate, and depositing a first gate region and a second gate region on the gate oxide layer. The first gate region is associated with the |
