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SanDisk Technologies, Inc Patents
Assignee:
SanDisk Technologies, Inc
Address:
Plano, TX
No. of patents:
240
Patents:


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Patent Number Title Of Patent Date Issued
RE43417 Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND May 29, 2012
A NAND flash memory structure with a wordline or control gate that provides shielding from Yupin effect errors and generally from potentials in adjacent strings undergoing programming operations with significant variations in potential.
D656122 Media player March 20, 2012
8590037 Managing host application privileges November 19, 2013
A method and system of controlling access to a hardware or software feature provided by a host is disclosed. An application seeking authorization to access a feature transmits a credential and an index to a host agent within the host. The index is associated with the requested featur
8582381 Temperature based compensation during verify operations for non-volatile storage November 12, 2013
A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the co
8580639 Method of making ultrahigh density vertical NAND memory device November 12, 2013
Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantial
8576624 On chip dynamic read for non-volatile storage November 5, 2013
Dynamically determining read levels on chip (e.g., memory die) is disclosed herein. One method comprises reading a group of non-volatile storage elements on a memory die at a first set of read levels. Results of the two most recent of the read levels are stored on the memory die. A c
8575739 Col-based semiconductor package including electrical connections through a single layer leadfram November 5, 2013
A semiconductor package is disclosed including a leadframe, memory die and controller die, one or more of which are customized to facilitate electrical connection of the memory and controller die bond pads to the contact pads of the host device via the leadframe. By customizing one or
8575724 Semiconductor device having under-filled die in a die stack November 5, 2013
A semiconductor device including a semiconductor die in a die stack under-filled with a film. Once the semiconductor die are formed, they may be stacked and interconnected. The interconnection may leave a small space between semiconductor die in the die stack. This space is advantage
8575000 Copper interconnects separated by air gaps and method of making thereof November 5, 2013
A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps i
8570810 Intelligent control of program pulse for non-volatile storage October 29, 2013
To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached.
8566695 Controlling access to digital content October 22, 2013
Method for utilizing digital content is provided. The method includes controlling a throughput rate for utilizing the digital content by an accessing system, wherein the throughput rate is associated with information related to the digital content stored as a file.
8566671 Configurable accelerated post-write read to manage errors October 22, 2013
Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less ro
8566504 Dynamic metablocks October 22, 2013
A nonvolatile block erasable memory array links erase blocks together for programming with high parallelism as a metablock. Erase blocks are operated in banks, with each bank having a dedicated bus and controller. Sub-metablocks of different metablocks, in different banks, are accessed
8561295 Method of adapting an expresscard slot for smaller form factor memory compatibility October 22, 2013
An adapter assembly is disclosed that enables a memory card having a smaller length than a standard ExpressCard to be compatible with the standard ExpressCard slot. The adapter assembly includes an adapter having side rails configured to disable the ExpressCard slot ejector mechanism
8301912 System, method and memory device providing data scrambling compatible with on-chip copy operatio October 30, 2012
Data scrambling techniques implemented externally to a flash memory device are disclosed which can be used in concert with flash memory on-chip copy functionality operating internally to the flash device, thus supporting high performance copying operations. All the data stored in the
8301826 Adaptive mode switching of flash memory address mapping based on host usage characteristics October 30, 2012
In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance
8300473 Non-volatile memory with improved sensing by reducing source line current October 30, 2012
One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference s
8300472 Low noise sense amplifier array and method for nonvolatile memory October 30, 2012
In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a
8300459 Non-volatile memory and method for power-saving multi-pass sensing October 30, 2012
A non-volatile memory device and power-saving techniques capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during sensing, which is included in read, and program/verify operations. A se
8300458 Nonvolatile memory with correlated multiple pass programming October 30, 2012
A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are correlated. Each programming pass employs a programming voltage in the form of a staircase pulse
8300457 Non-volatile memory and method with reduced neighboring field errors October 30, 2012
A memory device and a method thereof allow programming and sensing a plurality of memory cells in parallel in order to minimize errors caused by coupling from fields of neighboring cells and to improve performance. The memory device and method have the plurality of memory cells linked by
8296752 Implementation of in-system programming to update firmware on memory cards October 23, 2012
Methods and apparatus for efficiently enabling firmware associated with a flash memory card to be updated are disclosed. According to one aspect of the present invention, a method for updating firmware associated with a memory storage device includes providing new firmware to a host and
8296498 Method and system for virtual fast access non-volatile RAM October 23, 2012
A method of writing data to a non-volatile memory with minimum units of erase of a block, a page being a unit of programming of a block, may read a page of stored data addressable in a first increment of address from the memory into a page buffer, the page of stored data comprising an
8295085 Programming non-volatile memory with high resolution variable initial programming pulse October 23, 2012
Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming processes operate to program at least a subset of the non-volatile storage elements to a respective set of target conditions using program pulses. At least a subset
8294509 Charge pump systems with reduction in inefficiencies due to charge sharing between capacitances October 23, 2012
Improvements in the efficiency of two charge pump designs are presented. As a charge pump switches between modes, capacitances are charged. Due to charge sharing between capacitances, inefficiencies are introduced. Techniques for reducing these inefficiencies are presented for two di
8294251 Stacked semiconductor package with localized cavities for wire bonding October 23, 2012
A semiconductor die and a low profile semiconductor package formed therefrom are disclosed. The semiconductor package may include at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cav
8292177 Optimized non-volatile storage systems October 23, 2012
A memory card that adapts its operation according to the application to which it applied or the conditions under which it is operated. This allows the card to dynamical self optimize. In a first set of embodiments, the card uses host profiling where it will learn about the host durin
8291151 Enhanced host interface October 16, 2012
A memory system that is compatible with hosts using different protocols includes protocol adapters for the different protocols. Protocol adapters allow a common backend system to be used for data that is provided in different formats. A protocol adapter generates responses to a host and
8289418 Removable data storage device with interface to receive image content from a camera October 16, 2012
Systems and methods of receiving image content in a first format and storing converted image content in a second format are disclosed. A method includes receiving image content in a first format from a camera at an interface of a data storage device that includes a controller coupled
8288293 Integrated circuit fabrication using sidewall nitridation processes October 16, 2012
Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an
8288225 Method of reducing coupling between floating gates in nonvolatile memory October 16, 2012
A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structu
8286156 Methods and apparatus for performing resilient firmware upgrades to a functioning memory October 9, 2012
This invention relates generally to methods and computer readable media for upgrading firmware stored in a non-volatile memory, in phases, and restoring firmware in-situ to compensate for failed firmware upgrades. In various embodiments, methods and computer readable media can upgrade an
8284609 Compensation of non-volatile memory chip non-idealities by program pulse adjustment October 9, 2012
To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programmi
8284606 Compensating for coupling during programming October 9, 2012
Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate
8283664 Disguising test pads in a semiconductor package October 9, 2012
A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical test of the completed package. The test pads are formed in shapes such as letters or objec
8283228 Method of making ultrahigh density vertical NAND memory device October 9, 2012
Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantial
8278203 Metal control gate formation in non-volatile storage October 2, 2012
Methods for fabricating control gates in non-volatile storage are disclosed. When forming stacks for floating gate memory cells and transistor control gates, a sacrificial material may be formed at the top of the stacks. After insulation is formed between the stacks, the sacrificial
8275953 Methods for forcing an update block to remain sequential September 25, 2012
A method for operating a memory system is provided. In this method, a sequential update block and preexisting data associated with the sequential update block are provided. Here, an option to convert the sequential update block to a chaotic update block also is provided. A write comm
8274838 Programming non-volatile memory with bit line voltage step up September 25, 2012
Threshold voltage distributions in a non-volatile memory device are narrowed, and/or programming time is reduced, using a programming technique in which the bit line voltage for storage elements having a target data state is stepped up, in lock step with a step up in the program volt
8274831 Programming non-volatile storage with synchronized coupling September 25, 2012
A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process for programming includes raising voltages for a set of word lines connected a group of connect
8270217 Apparatus for reducing the impact of program disturb September 18, 2012
The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as "program disturb." A system is proposed for programming and/or reading non-volatile sto
8266711 Method for controlling information supplied from memory device September 11, 2012
A memory storing public and confidential information is removably connected to a host device. General information on data stored in memory devices is accessible to the host device without authentication. Only a portion of confidential information stored in the memory device is access
8266485 Test mode soft reset circuitry and methods September 11, 2012
A soft-function trigger state machine includes state machine logic defined to use a scan-in waveform to sample a scan-clock waveform to obtain a sampled data pattern. The state machine logic is defined to compare the sampled data pattern to a soft action pattern to determine whether
8266391 Method for writing data of an atomic transaction to a memory device September 11, 2012
A method for writing data to a memory device is disclosed. In one embodiment, data of an atomic transaction is written to a first memory in a memory device. A determination is made regarding whether all of the data of the atomic transaction was written to the first memory. The data o
8266366 Memory device operable in read-only and write-once, read-many (WORM) modes of operation September 11, 2012
One-time programmable (OTP) and write-once read-many (WORM) memory devices and methods for use therewith are provided. These embodiments can be used to provide compatibility between a memory device that uses an OTP (or few-time programmable (FTP)) memory array and host devices that use a
8264890 Two pass erase for non-volatile storage September 11, 2012
Techniques are disclosed herein for erasing non-volatile memory cells. A subset of the memory cells are pre-conditioned prior to erase. The pre-conditioning alters the threshold voltage of the memory cells in a way that may help make later calculations more accurate. As an example, m
8263465 Method of forming memory with floating gates including self-aligned metal nanodots using a coupl September 11, 2012
Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having
8261136 Method and device for selectively refreshing a region of a memory of a data storage device September 4, 2012
A method and device for selectively refreshing a region of a non-volatile memory of a data storage device is disclosed. In a particular embodiment, a method is disclosed that includes comparing a time stamp received from a host device to a first time stamp retrieved from a data storage d
8255773 System and method of tracking error data within a storage device August 28, 2012
Systems and methods of tracking error data are disclosed. A method includes receiving a first checksum associated with error locations of a first error correction code operation and receiving a second checksum associated with error locations of a second error correction code operatio
8255655 Authentication and securing of write-once, read-many (WORM) memory devices August 28, 2012
These embodiments relate to authentication and securing of write-once, read-many (WORM) memory devices. In one embodiment, a memory device comprises a controller operable in first and second modes of operation after stored security information is validated, wherein in the first mode
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