| Patent Number |
Title Of Patent |
Date Issued |
| RE38657 |
Current limitation programmable circuit for smart power actuators |
November 23, 2004 |
| A circuit for limitation of maximum current delivered by a power transistor comprises: a network for detection of the current delivered by the power transistor which generates a first electrical signal; a reference network for generating a reference current proportional to a resistor and |
| RE38510 |
Manufacturing process for a monolithic semiconductor device comprising at least one transistor o |
May 4, 2004 |
| The device uses the horizontal insulating region and the buried layer as the power transistor base and emitter respectively. An epitaxial growth is interposed between the two diffusions needed to form the aforesaid regions and those needed to create the base and the emitter of the transi |
| RE38387 |
Multiplier circuit for multiplication operation between binary and twos complement numbers |
January 13, 2004 |
| A multiplier circuit which multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating circuits provide partia |
| RE38166 |
Circuit and method for reading a memory cell that can store multiple bits of data |
July 1, 2003 |
| A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2.sup.n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that |
| RE38154 |
Method and circuit for detecting a fault in a clock signal for microprocessor electronic devices |
June 24, 2003 |
| An electronic device including a microprocessor, a circuit generating a clock signal, and memories of both the volatile type and the non-volatile type, incorporates a circuit for generation of a reset signal capable of detecting a stop in the oscillation of said clock signal and generati |
| RE37898 |
Self-oscillating switching power supply with output voltage regulated from the primary side |
November 5, 2002 |
| Regulation of the output voltage of a power supply employing a flyback-type self-oscillating DC--DC converter employing a transformer. The primary winding circuit of the transformer senses a current recirculation loop for discharging the energy cyclically stored in an auxiliary winding o |
| RE37707 |
Leadframe with heat dissipator connected to S-shaped fingers |
May 21, 2002 |
| An improved leadframe for packages of integrated power devices which, by virtue of its configuration, allows to press the dissipator on the bottom of the shell during the molding of the plastic case, without the dissipator having exposed portions of its inner face (which is in contact |
| RE37440 |
Memory for programmable digital filter |
November 6, 2001 |
| The filter includes an arithmetical chain of parallel adders alternated with delay elements, and a memory constituted by lines of one-bit cells. Each line is addressable by a decoder controlled by a digital signal to be filtered; each line of memory contains side by side values which |
| RE37416 |
Method for manufacturing a modular semiconductor power device |
October 23, 2001 |
| The components used in the method comprise a heat-dissipating base plate, one or more three-layer plates (the top layer consisting of copper plates and strips) and a one-piece frame designed to constitute the terminals. After the chips have been soldered onto the upper plates and connect |
| RE37308 |
EEPROM memory cell with a single level of polysilicon programmable and erasable bit by bit |
August 7, 2001 |
| The cell is formed of a selection transistor, a detection transistor and a tunnel condenser. The detection Transistor has its own control gate formed with an n.sup.+ diffusion which is closed and isolated from those of the other cells of the same memory. |
| RE36998 |
Circuit for limiting the output voltage of a power transistor |
December 26, 2000 |
| A circuit for limiting the output voltage from a power transistor connected in series with a resonant load between a voltage supply and a voltage reference, ground, is disclosed. The circuit includes a semiconductor junction element, in particular a diode of the SCR type, having an anode |
| RE36026 |
Programmable device for storing digital video lines |
January 5, 1999 |
| A programmable device for storing digital video lines, being of a type intended for use in TV sets with digital frame scan features whereby a video line is sample coded in a digital signal, comprises at least one pair of memories each adapted to contain the code of one video line, and a |
| 7460581 |
Method for transmitting signals using antenna diversity, for instance in mobile communication sy |
December 2, 2008 |
| Encoded digital symbols are transmitted via a first pair of antennas and at least one second pair of antennas. The sets of symbols used for the transmission via the second pair of antennas are re-ordered temporally into subsets of symbols with respect to the symbols used for the first |
| 7459890 |
Method and circuit for controlling an electric power plant |
December 2, 2008 |
| A control circuit is for an electric power plant including an asynchronous generator of an AC voltage, a motor to rotate a rotor of the asynchronous generator as a function of a first control signal of a developed motor torque, and a bank of capacitors coupled to the asynchronous generat |
| 7459771 |
Assembly structure for electronic power integrated circuit formed on a semiconductor die and cor |
December 2, 2008 |
| An assembly structure for an electronic integrated power circuit, which circuit is fabricated on a semiconductor die having a plurality of contact pads associated with said integrated circuit and connected electrically to respective leads of said structure, wherein a shield element i |
| 7459387 |
Semiconductor electronic device and method of manufacturing thereof |
December 2, 2008 |
| A semiconductor electronic device includes a die of semiconductor material and a support. The die of semiconductor material includes an integrated electronic circuit and a plurality of contact pads associated with the electronic circuit and connected electrically to the support by wire |
| 7456637 |
Measurement alignment system to determine alignment between chips |
November 25, 2008 |
| An embodiment of the present invention relates to a alignment measurement system for measuring alignment between a plurality of chips of a device, the chips being assembled in a three-dimensional stacking configuration and equipped with at least an integrated capacitive sensor, including |
| 7456508 |
Hosting structure of nanometric elements and corresponding manufacturing method |
November 25, 2008 |
| A hosting structure of nanometric components is described comprising a substrate, a first multi-spacer level comprising a first plurality of spacers including first conductive spacers parallel to each other, and at least a second multi-spacer level realized above said first multi-spacer |
| 7454954 |
Knocking presence evaluation circuit for an internal combustion engine, knocking identification |
November 25, 2008 |
| A knocking presence evaluation circuit in an internal combustion engine having a pressure sensor facing a combustion chamber for each cylinder in the engine and suitable to produce a pressure signal, the circuit having an input terminal; a processing block connected by the input terminal |
| 7454091 |
Integrated optical network with controlled optical beam deflection and optical transmitter |
November 18, 2008 |
| Integrated optical network comprising: an array of optical waveguides having respective output ends defining a array of radiating elements, wherein said guides receive respective optical input signals and output said optical signals from said radiating elements to form an optical b |
| 7452713 |
Process for manufacturing a microfluidic device with buried channels |
November 18, 2008 |
| A process for manufacturing a microfluidic device, including the steps of: forming at least one channel in a semiconductor material body; forming a dielectric diaphragm above the channel, for closing the channel; and forming heating elements for providing thermal energy inside the channe |
| 7450663 |
Interpolation for use in channel estimation |
November 11, 2008 |
| A method for the estimation of the transfer function of a transmission channel in a receiving system of UMTS type envisages the computation of a plurality of channel coefficients, included among known channel coefficients corresponding to pilot symbols, through the reiteration of an |
| 7450332 |
Free-fall detection device and free-fall protection system for a portable electronic apparatus |
November 11, 2008 |
| In an integrated free-fall detection device for a portable apparatus an acceleration sensor generates acceleration signals correlated to the components of the acceleration of the portable apparatus along three detection axes. A dedicated purely hardware circuit connected to the accel |
| 7449935 |
Driven circuit of an emitter switching configuration to control the saturation level of a power |
November 11, 2008 |
| A drive circuit for an emitter switching configuration of transistors having a cascode connection of a power bipolar transistor and of a power MOS transistor control the saturation level of the configuration in applications which provide highly variable collector currents. The drive |
| 7447716 |
Data coding method and corresponding data processing unit having a coding/decoding circuit |
November 4, 2008 |
| The method of coding data within a data processing unit includes a representation as twos-complement and a coded representation of the data. The coded representation is a semi-negated representation. A data processing unit includes a memory device connected bidirectionally to a data |
| 7447283 |
Method for automatic gain control, for instance in a telecommunication system, device and comput |
November 4, 2008 |
| A method for automatic gain control of an output signal generated from an input signal includes measuring power of the output signal. Measuring power of the output signal includes setting at least one power threshold, measuring a rate of crossing of the at least one power threshold by th |
| 7447103 |
Row decoder circuit for electrically programmable and erasable non volatile memories |
November 4, 2008 |
| The invention relates to a row decoder circuit for non volatile memory devices of the electrically programmable and erasable type, for example of the Flash EEPROM type having a NOR architecture. The proposed row decoder circuit allows to carry out the erasing step very quickly, for e |
| 7446968 |
Method for using a minimum latency loop for a synchronization system in a hard disk drive |
November 4, 2008 |
| The method and architecture improve the robustness of a synchronization system through a minimum latency loop, for Hard Disk Drives (HDD), for example, wherein synchronous detection processing is performed for timing recovering of a correct sampling phase and frequency and by a first |
| 7446611 |
Fully differential amplifier device with output-common-mode feedback and control method thereof |
November 4, 2008 |
| A fully differential amplifier device includes a first input and a second input, a first output and a second output, and a differential input stage, provided with a first input transistor and a second input transistor. The first input and the first output and the second input and the |
| 7446003 |
Manufacturing process for lateral power MOS transistors |
November 4, 2008 |
| A process manufactures power MOS lateral transistors together with CMOS devices on a semiconductor substrate. The process forms a lateral MOS transistor having a gate electrode on the semiconductor region, a source comprising a first highly doped portion aligned with the gate electrode |
| 7443908 |
Low complexity detection in digital receivers |
October 28, 2008 |
| A receiver for receiving digital signals exposed to intersymbol interference as well as multiple access interference the method including linearly detecting said signals by combating said intersymbol interference by equalizing said received digital signals as well as mitigating said |
| 7440839 |
Method and associated device for sensing the air/fuel ratio of an internal combustion engine |
October 21, 2008 |
| A method of sensing the air/fuel ratio in a combustion chamber of an internal combustion engine that may be easily implemented by a respective low-cost device includes a pressure sensor and a learning machine that generates a sensing signal representing the air/fuel ratio by processing |
| 7440631 |
Method of compressing digital images acquired in CFA format |
October 21, 2008 |
| A method of compressing digital images acquired in CFA format that utilizes optimized quantization matrices. The method, basing itself on the statistical characterization of the error introduced during the processing phase that precedes compression, appropriately modifies the coeffic |
| 7440625 |
Method and apparatus for decoding compressed and encoded digital images |
October 21, 2008 |
| A method for decoding-decompressing a compressed-encoded digital data sequence relating to at least one compressed-encoded digital image and for providing at least one respective decoded-decompressed digital image. |
| 7440297 |
Fault detection for loss of feeback in forced switching power supplies with power factor correct |
October 21, 2008 |
| A device corrects the power factor in forced switching power supplies and includes a converter and a control device to obtain a regulated voltage on an output terminal. The control device comprises an error amplifier having an inverting terminal (Vout) and a non-inverting terminal re |
| 7437933 |
Micro-electro-mechanical structure having electrically insulated regions and manufacturing proce |
October 21, 2008 |
| Micro-electro-mechanical structure formed by a substrate of semiconductor material and a suspended mass extending above the substrate and separated therefrom by an air gap. An insulating region of a first electrically insulating material extends through the suspended mass and divides it |
| 7436963 |
Process for generating codes for CDMA communications, system and computer program product theref |
October 14, 2008 |
| To generate the main scrambling code of order N and the secondary scrambling code of order K within the set identified by the primary scrambling code of order N, a first m-sequence and a second m-sequence are generated using Fibonacci linear feedback shift registers. The first m-sequ |
| 7436441 |
Method for down-scaling a digital image and a digital camera for processing images of different |
October 14, 2008 |
| A digital camera for capturing and processing images of different resolutions and a corresponding method for down-scaling a digital image are provided. The method includes forming an image of a real scene on an image sensor that is made up of a plurality of pixels arranged in a matri |
| 7432587 |
Integrated device including connections on a separate wafer |
October 7, 2008 |
| An integrated semiconductor device includes semiconductor regions and isolation regions in a first wafer of semiconductor material, and, on a second wafer of semiconductor material, interconnection structures. Plug elements provide electrical and mechanical coupling between the first and |
| 7432120 |
Method for realizing a hosting structure of nanometric elements |
October 7, 2008 |
| Method for manufacturing a hosting structure of nanometric elements comprising the steps of depositing on an upper surface of a substrate, of a first material, a block-seed having at least one side wall. Depositing on at least one portion of sad surface and on the block-seed a first |
| 7425857 |
Time-delay circuit |
September 16, 2008 |
| A time delay logic comprises a first stage with an inverter, a capacitor connected to the input terminal of the inverter, a constant current generator and an electronic switch controlled by an input pulse. The capacitor begins to charge at a predetermined edge of the input pulse and |
| 7424068 |
Method and system for coding/decoding signals and computer program product therefor |
September 9, 2008 |
| A method for decoding signals with encoded symbols over a symbol interval that modulate a carrier. The method includes phase locking the signal to be decoded to obtain a phase-locked signal. The value assumed by the phase-locked signal on at least one subinterval in each symbol interval |
| 7423890 |
Push-pull converter, in particular for driving cold-cathode fluorescent lamps |
September 9, 2008 |
| A push-pull converter has a transformer provided with a primary winding and a secondary winding. A capacitive element is connected between the input terminals of the primary winding, and two switch elements are arranged between a respective input terminal of the primary winding throu |
| 7422926 |
Self-aligned process for manufacturing phase change memory cells |
September 9, 2008 |
| A process for manufacturing phase change memory cells includes the step of forming a heater element in a semiconductor wafer and a storage region of a phase change material on and in contact with the heater element. In order to form the heater element and the phase change storage region |
| 7421904 |
Assembly of an integrated device enabling a facilitated fluidic connection to regions of the dev |
September 9, 2008 |
| Described herein is an assembly of an integrated device and of a cap coupled to the integrated device; the integrated device is provided with at least a first and a second region to be fluidically accessed from outside, and the cap has an outer portion provided with at least a first |
| 7419876 |
Method for manufacturing non-volatile memory devices integrated in a semiconductor substrate |
September 2, 2008 |
| A method manufactures non-volatile memory devices integrated on a semiconductor substrate and including a matrix of non-volatile memory cells and associated circuitry. The manufacturing method includes: forming a plurality of electrodes of the matrix memory cells, each electrode incl |
| 7417900 |
Method and system for refreshing a memory device during reading thereof |
August 26, 2008 |
| A refresh circuit for refreshing a memory device is proposed. The refresh circuit includes: reading means for reading a set of memory cells, the reading means including means for applying a biasing voltage having a substantially monotone time pattern to the memory cells and to a set of |
| 7417460 |
Multi-standard transmitter |
August 26, 2008 |
| A multi-standard transmitter includes a differential stage that includes a current generator transistor; first and second transistors connected between a first node and the generator transistor and having respective control terminals connected to a first input terminal, the first and |
| 7417298 |
High voltage insulated-gate transistor |
August 26, 2008 |
| An insulated-gate transistor, includes a semiconductor material layer having a front surface, a body region, an insulated gate disposed over the body region with interposition of a gate dielectric, and a source and drain region, the source region formed in the body region and the drain |
| 7414902 |
Semiconductor memory device with information loss self-detect capability |
August 19, 2008 |
| A semiconductor memory device, including a plurality of programmable memory cells each one adapted to be brought into one among at least a first status and a second status, said plurality of memory cells including memory cells intended to store data, and means for accessing the memor |
