| Patent Number |
Title Of Patent |
Date Issued |
| RE37124 |
Ring oscillator using current mirror inverter stages |
April 3, 2001 |
| A ring oscillator having an odd number of single ended stages, each stage including two transistors connected as a current mirror. The stage provides for low-voltage performance and improved process tolerance characteristics. |
| 7441109 |
Computer system with a debug facility for a pipelined processor using predicated execution |
October 21, 2008 |
| A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is execute |
| 7437514 |
Cache system |
October 14, 2008 |
| A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by |
| 7406581 |
Speculative instruction load control |
July 29, 2008 |
| A method and system for validating speculative load operations. The system identifies speculative load operations that might be executed in a code sequence and after translating the virtual address of the speculative load to a physical address, a speculative load control unit is used to |
| 7406113 |
Integrated circuit for code acquisition |
July 29, 2008 |
| A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, sample reducer combines samples of a received signal for correlation with a locally generated |
| 7403558 |
Integrated circuit for code acquisition |
July 22, 2008 |
| A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, a memory arrangement comprising two circulating shift registers circulates samples of a receiv |
| 7398440 |
Tap multiplexer |
July 8, 2008 |
| An integrated circuit comprising: a plurality of portions, each portion including test control circuitry; at least one test input arranged to receive test signals; and a multiplexer between the at least one test input and the test control circuitry, the multiplexer having a least one |
| 7395296 |
Circuitry and method for performing non-arithmetic operations |
July 1, 2008 |
| Circuitry is provided for performing a non-arithmetic operation in relation to at least one number. The circuitry includes a first part for carrying out the non-arithmetic operation in relation to the at least one number, the first part providing a result. A second part is arranged to |
| 7392171 |
Test bench generator for integrated circuits, particularly memories |
June 24, 2008 |
| A computer based test bench generator (1) for verifying integrated circuits specified by models in a Hardware Description Language includes a repository (10) storing a general set of self-checking tests applicable to the integrated circuits. A capability is provided for entering beha |
| 7391909 |
Data manipulation |
June 24, 2008 |
| A method for performing a reordering operation on a matrix of input data values, the method comprising: loading the data values into a computer store by forming a plurality of data strings, each data string comprising a plurality of data sub-strings and each data sub-string representing |
| 7383481 |
Method and apparatus for testing a functional circuit at speed |
June 3, 2008 |
| An integrated circuit including functional circuitry; test circuitry connected to the functional circuitry, wherein the test circuitry is arranged to control the testing of the functional circuitry; and clock signal generating circuitry connected to both the functional circuitry and |
| 7372906 |
Compression circuitry for generating an encoded bitstream from a plurality of video frames |
May 13, 2008 |
| Data is discrete cosine transformed and streamed to a processor where quantized and inverse quantized blocks are generated. A second streaming data connection streams the inverse quantized blocks to an inverse discrete cosine transform block to generate reconstructed prediction error |
| 7366938 |
Reset in a system-on-chip circuit |
April 29, 2008 |
| An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a soft reset signal for resetting the second circuitry, the integrated circuit further including |
| 7356708 |
Decryption semiconductor circuit |
April 8, 2008 |
| A semiconductor integrated circuit having a plurality of selectable pathways inter-connected to data sources and data destinations; a cryptographic circuit connected to the selectable pathways to selectively receive data from at least one of the data sources, to decrypt or encrypt th |
| 7353508 |
Method, apparatus and article for generation of debugging information |
April 1, 2008 |
| Call frame information is used by debugging software. It records how to restore the parent stack frame at any point during execution of a program. It is normally generated during compilation and stored in the executable in a compressed format, consisting of sequences of instructions |
| 7346822 |
Integrated circuit |
March 18, 2008 |
| An integrated circuit including test circuitry, the test circuitry including a counter for counting clock signals and having an output for providing a control signal. The counter being arranged to have an internal state, and the counter being arranged to change the control signal on |
| 7325018 |
Design flow checker |
January 29, 2008 |
| A method is disclosed for operating a computer system in order to validate data stored in a plurality of data files in a database. Each of the data files have an associated file type and are arranged in a plurality of data stores in the database. At least one of the data files is a data |
| 7307631 |
Computer graphics |
December 11, 2007 |
| An image is rendered which includes at least one light source, a first, shadow-casting object with a second, shadow-receiving object located on the side of the first shadow-casting object remote from said at least one light source. A shadow mask is generated which identifies for each of |
| 7299462 |
Relocation format for linking |
November 20, 2007 |
| A method of preparing an executable program from a plurality of object code modules, at least one of said object code modules including section data specifying a plurality of functions associated with relocation instructions, at least some of which functions are called in the executa |
| 7253816 |
Computer graphics acceleration method and apparatus for evaluating whether points are inside a t |
August 7, 2007 |
| A computer graphics accelerator apparatus and method determines whether a pixel at predetermined pixel co-ordinates in an area being rasterized is within a triangle defining a sub-area of the area. The coordinate system in relation to which the triangle is defined is translated such that |
| 7248602 |
Flexible filtering |
July 24, 2007 |
| A circuit and method for demultiplexing in a receiver a digital data stream including at least two types of data. In one particular application, such a receiver is used in a television system having a digital set-top-box receiver. A first control circuit extracts a packet identifier |
| 7243202 |
Searching for packet identifiers |
July 10, 2007 |
| A method of locating packet identifiers held in respective memory locations in a memory, the method comprising receiving a plurality of packets, each packet including a packet identifier, searching said memory locations in a sequence to compare an incoming packet identifier with pack |
| 7234089 |
Tristate buses |
June 19, 2007 |
| Circuitry for testing and implementing a distributed tristate bus, the circuitry being configured in the testing mode, when a first signal is supplied to a first enable input and a test enable signal is operative, the cascade circuitry outputs a cascade out signal to the cascade input |
| 7216342 |
Code generation |
May 8, 2007 |
| A method of linking a plurality of object files to generate an executable program, the method comprises identifying in the object files at least one routine to be locked into a cache when the program is executed, locating said routine at a set of memory addresses which man onto a set |
| 7200843 |
Retrieval of symbol attributes |
April 3, 2007 |
| A method of linking a plurality of object code modules to form an executable program, each object code module having section data, a set of relocation instructions and one or more symbols, each symbol having a plurality of attributes associated therewith, wherein the relocation instr |
| 7191416 |
System and method for modifying integrated circuit hold times |
March 13, 2007 |
| A method of arranging an integrated circuit to correct for hold time errors comprises fixing the position of existing cells in a design, determining hold time errors required to be corrected and placing buffer cells in spaces in the existing design. By placing buffer cells in spaces |
| 7187774 |
Mute switch |
March 6, 2007 |
| A mute switch including a field effect transistor receiving a mute control signal at its gate for selectively supplying an audio signal from an input node to an output node. A bipolar transistor is connected between the input node and the FET for reducing the voltage level of the audio |
| 7174357 |
Circuitry for carrying out division and/or square root operations requiring a plurality of itera |
February 6, 2007 |
| Circuitry for carrying out an arithmetic operation requiring a plurality of iterations, such as division or square root operations, utilizes N sets of iteration circuitry arranged one after the other so that at least one of the sets of iteration circuitry receives an output from a pr |
| 7171599 |
Field programmable device |
January 30, 2007 |
| A field programmable device is disclosed, including a plurality of logic blocks; a plurality of connections connecting the logic blocks; configuration circuitry for outputting configuration data for programming the field programmable device, the configuration circuitry providing at l |
| 7170512 |
Index processor |
January 30, 2007 |
| A graphic processor having an index processing unit for pre-processing a list of vertices making up a three-dimensional image. The method of pre-processing comprising the following steps. First, decomposing the three-dimensional image into a plurality of primitive elements each defin |
| 7167887 |
Circuitry for carrying out square root and division operations |
January 23, 2007 |
| The invention provides circuitry for carrying out a square root operation and a division operation. The circuitry utilizes common iteration circuitry for carrying out a plurality of iterations and means for identifying if an square root operation or a division operation is to be perf |
| 7155709 |
Displaying user readable information during linking |
December 26, 2006 |
| A method of forming an executable program from a plurality of object code modules where each object code module includes a plurality of relocation instructions having at least one information output relocation with a field indicating information to be output. The method includes reading |
| 7155707 |
Compiling computer programs including branch instructions |
December 26, 2006 |
| This patent describes a method of compiling a computer program from a sequence of computer instructions including a plurality of first, set branch, instructions which each identify a target address for a branch and a plurality of associated second, effect branch instructions which ea |
| 7143311 |
Interrupt handler for a data processor |
November 28, 2006 |
| A data processor formed on a single integrated circuit and capable of connection to an external memory, the data processor including: a central processing unit; a local memory including a debug memory area; a plurality of interrupt inputs; an interrupt handler coupled to the interrup |
| 7134058 |
Memory circuit scan arrangement |
November 7, 2006 |
| A semiconductor integrated circuit comprises a plurality of combinational logic components, a memory and a testing arrangement for configuring the memory prior to testing the combinational logic components using one or more scan chains. The arrangement includes a bit pattern generator fo |
| 7133817 |
State coverage tool |
November 7, 2006 |
| A method of verifying a digital hardware design simulated in a hardware design language (HDL). States to be verified are defined, including signal values for each component within the hardware design. A test is applied to the hardware design, such that traces of internal signals with |
| 7127711 |
Forming an executable program |
October 24, 2006 |
| A linker is described and the method of forming an executable program from object code modules using the linker. The linker uses a linker control language in the form of an ordered sequence of relaxation instructions. The relaxation instructions include a jump relaxation instruction whic |
| 7072400 |
Inverse zigzag scanning of a matrix of video data values and manipulation |
July 4, 2006 |
| A decoding apparatus for decoding digital video data, in a data memory including registers, each register being capable of storing a data strings with a plurality of data sub-strings such that the data sub-strings are not individually addressable; an input for receiving compressed vi |
| 7062634 |
Processor and a method for handling and encoding no-operation instructions |
June 13, 2006 |
| A processor is described in which the need to encode no-operation instructions (nops) in the program is minimised by providing a device for generating nops in response to information encoded in operative instructions. |
| 7050436 |
Device and method for processing a stream of data |
May 23, 2006 |
| This invention relates to a device and method for producing a stream of data. The device receives a stream of data as an input and includes means for identifying a portion of the input stream and outputting the identified portion. The device also includes means for selecting a furthe |
| 7047245 |
Processing system |
May 16, 2006 |
| A processing system which comprises means for storing a plurality of items defining a queue, pointer means having a first pointer and a second pointer associated with the beginning of said queue and a second pointer associated with the back of said queue; at least one writer for adding |
| 7039831 |
Common stack system for a debugging device and method |
May 2, 2006 |
| During debugging of target system by a host system, s single stack is used for an exception by a set of applications running on the processor of the target. To achieve this, the stack is dynamically loaded by the host to a reserved memory region, and a vector of the target is set to poin |
| 7031903 |
Interface device |
April 18, 2006 |
| A communication device for a target integrated circuit chip having a digital processor, an on-chip emulator for controlling the digital processor and for collecting operation data from the digital processor for communicating to off-chip circuitry, and a target on-chip universal seria |
| 7010732 |
Built-in test support for an integrated circuit |
March 7, 2006 |
| Test circuitry for testing an integrated circuit, the integrated circuit being configurable to accept input data from stimulus scan cells and to provide output data to response scan cells, the test circuitry including stimulus circuitry for providing test data to the integrated circuit; |
| 7007272 |
Compiling computer programs including branch instructions |
February 28, 2006 |
| This patent describes a method of compiling a computer program from a sequence of computer instructions including a plurality of first, set branch, instructions which each identify a target address for a branch and a plurality of associated second, effect branch instructions which ea |
| 6996513 |
Method and system for identifying inaccurate models |
February 7, 2006 |
| A method and system for identifying an inaccurate model of a hardware circuit includes the steps of simulating a digital model and an analogue model of the circuit to provide first and second sets of simulation results respectively. For each result in the first and second sets of sim |
| 6990100 |
Packet conversion |
January 24, 2006 |
| A method of converting a packet of data from a source format to a target format, the packet including a type indicator and at least one data field, the method including the steps of storing a table for each packet type, each table including for each data field of that packet type a v |
| 6982573 |
Switchable clock source |
January 3, 2006 |
| A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a |
| 6973592 |
On-chip emulator communication |
December 6, 2005 |
| An integrated circuit chip comprising embedded digital processor and an on-chip emulation device coupled to said digital signal processor, said emulation device being operable to control said digital processor and to collect information about the operation of said digital processor, the |
| 6973591 |
On-chip emulator communication for debugging |
December 6, 2005 |
| A debugging system comprising a host computer system and a target device, said target device having an embedded digital processor on an integrated circuit chip, an on-chip emulation device coupled to said digital processor, the on-chip emulation device being operable to control said |
