| Patent Number |
Title Of Patent |
Date Issued |
| 5889713 |
Testing of embedded memory by coupling the memory to input/output pads using switches |
March 30, 1999 |
| A method and circuits for coupling a memory embedded in an integrated circuit to interconnect pads during a memory test mode is disclosed. The integrated circuit contains a processor, an embedded memory and a switching circuit for: (1) temporary coupling the interconnect pads of the |
| 5889515 |
Rendering an audio-visual stream synchronized by a software clock in a personal computer |
March 30, 1999 |
| A DVD CD-ROM player integrated with a personal computer is provided. When integrating a DVD CD-ROM with a personal computer, there are various problems that must be overcome. For example, the stream from the DVD CD-ROM utilizes a 27 MHz clock. However, a personal computer typically d |
| 5888908 |
Method for reducing reflectivity of a metal layer |
March 30, 1999 |
| A method is provided for reducing the reflectivity of a metal layer prior to photolithography. A thin buffer layer, such as oxide, can be deposited over the metal layer. A short plasma etch is performed in order to roughen, but not completely remove, the thin oxide layer. This roughened |
| 5887479 |
Liquid-level gauge driver circuit |
March 30, 1999 |
| A liquid level sensor unit outputs a voltage value, which corresponds to a measured liquid level, to an anti-slosh circuit that provides a fast timing rate during the initial condition of the circuit and a slow timing rate during the normal operation of the circuit. The anti-slosh circui |
| 5883844 |
Method of stress testing integrated circuit having memory and integrated circuit having stress t |
March 16, 1999 |
| An integrated circuit having enhanced testing capabilities and a method of testing an integrated circuit are provided. The integrated circuit preferably includes a substrate and a memory block on the substrate. The memory block preferably has a plurality of memory cells arranged in a |
| 5883838 |
Device and method for driving a conductive path with a signal |
March 16, 1999 |
| A signal driver receives an input signal and an enable signal, and generates an output signal from the input signal when the enable signal has an active state. When the enable signal has an inactive state, the signal driver draws substantially zero supply current regardless of the le |
| 5883544 |
Integrated circuit actively biasing the threshold voltage of transistors and related methods |
March 16, 1999 |
| An integrated circuit includes a plurality of MOSFETs having channels of a first conductivity type, and having active control of an effective threshold voltage of the MOSFETs to be less than an absolute value of an initial threshold voltage. In this embodiment, a first MOSFET has a c |
| 5883507 |
Low power temperature compensated, current source and associated method |
March 16, 1999 |
| An integrated circuit and method are provided for generating current for low power applications. The integrated circuit preferably includes a current generating circuit responsive to a supply voltage for generating a first reference current and a temperature compensating voltage controll |
| 5883479 |
BEMF rectification during power off to prevent parasitic effect |
March 16, 1999 |
| A circuit and method to clamp a node of a power device connected to a driving node of a polyphase d-c motor to a reference potential during a powering off of the drive includes a current mirror and a comparator. A first input of the comparator is connected to the reference potential, and |
| 5883008 |
Integrated circuit die suitable for wafer-level testing and method for forming the same |
March 16, 1999 |
| A semiconductor integrated-circuit die includes a substrate of semiconductor material that has an edge. A conductive layer is disposed on the substrate, and a first insulator layer is disposed between the said substrate and the conductive layer. A functional circuit is disposed in th |
| 5881010 |
Multiple transistor dynamic random access memory array architecture with simultaneous refresh of |
March 9, 1999 |
| A four transistor dynamic memory cell architecture and refresh technique which allows for cell refresh to occur during a read operation. The access and memory transistors of the individual memory cells are fabricated with a relative width-to-length ratio such that it is sufficient to mer |
| 5880611 |
Reset circuit using comparator with built-in hysteresis |
March 9, 1999 |
| A comparator with a built-in offset is disclosed. The claimed comparator includes a bias current circuit, a differential input stage with the built-in of-set, and a hysteresis circuit. The built-in offset is generated by using a resistor in the differential input stage of the compara |
| 5877914 |
Amplifier output clamping scheme |
March 2, 1999 |
| An amplifier in which a clamping circuit is an integral part of the output stage structure is used as a voice coil driver for positioning the heads of a memory disk drive. The output stage, operating in class AB, comprises two bipolar transistors, the source and the sink transistors, ser |
| 5877541 |
Contact structure for improving photoresist adhesion on a dielectric layer |
March 2, 1999 |
| A method is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the integrated circuit. An interlevel dielectric layer is formed over the conformal dielectric |
| 5874769 |
Mosfet isolation structure with planar surface |
February 23, 1999 |
| A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A conductive layer is formed over a substrate. A silicon nitride layer is formed over the conductive layer. A photoresist layer is then formed and |
| 5872053 |
Method of forming an enlarged head on a plug to eliminate the enclosure requirement |
February 16, 1999 |
| The contact opening through an insulating layer is formed having a straight sidewall portion and a bowl shaped sidewall portion. The bowl shaped sidewall portion is near the top of the insulation layer to provide an enlarged diameter of the contact opening at the top relative to the |
| 5870330 |
Method of making and structure of SRAM storage cell with N channel thin film transistor load dev |
February 9, 1999 |
| An SRAM cell includes a pair of N channel transistors acting as inverting circuits, a pair of N channel transistors which perform the control function for the cell, and a pair of N channel thin film transistors in depletion mode with gate and source shorted to provide load devices for |
| 5869946 |
PWM control of motor driver |
February 9, 1999 |
| Methods and apparatuses are provided for use in driving a multiple-phase brushless motor. The methods and apparatuses include generating a slewed phase control signal for each phase of the motor. The slewed phase control signals are substantially proportional to a speed control signal du |
| 5869388 |
Method of gettering using doped SOG and a planarization technique |
February 9, 1999 |
| A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A gate electrode is formed over a substrate having source/drain regions adjacent to the gate electrode and in the substrate. A silicon dioxide layer is |
| 5869371 |
Structure and process for reducing the on-resistance of mos-gated power devices |
February 9, 1999 |
| A VDMOS structure with an added n- doping component, and a LOCOS oxide self-aligned to it, at the surface extension of the drain. The additional shallow n- component permits the body diffusion to be heavier, and hence reduces the risk of latchup. |
| 5869175 |
Integrated circuit structure having two photoresist layers |
February 9, 1999 |
| A structure formed during processing of an integrated circuit. Two layers of photoresist are formed over a conductive layer to be patterned. The lower layer is thinner than the upper layer, and is dyed to have a lower transmittance. Both layers are used as a masking pattern for the u |
| 5866998 |
Circuit for improving back emf detection in pulse width modulation mode |
February 2, 1999 |
| A power-switched driver circuit for a disc drive that provides accurate back emf detection in PWM mode. In one embodiment, a power transistor is coupled between the low side drivers and ground. During the off time of a PWM cycle, all of the high side drivers are off and the current r |
| 5866797 |
Liquid level gauge interface system having dynamic offset |
February 2, 1999 |
| A liquid level sensor unit outputs a voltage value which corresponding to a measured liquid level to an improved anti-slosh circuit that provides a fast timing rate during the initial condition of the circuit and a slow timing rate during the normal operation of the circuit. The improved |
| 5864696 |
Circuit and method for setting the time duration of a write to a memory cell |
January 26, 1999 |
| A circuit and method for varying the time of a write cycle. A variable timer circuit is provided coupled to a write simulation circuit. The write simulation circuit receives a signal from a start write sensing circuit indicating that data is being written to memory cells of the array. Th |
| 5861660 |
Integrated-circuit die suitable for wafer-level testing and method for forming the same |
January 19, 1999 |
| A semiconductor integrated-circuit die includes a substrate of semiconductor material that has an edge. A conductive layer is disposed on the substrate, and a first insulator layer is disposed between the said substrate and the conductive layer. A functional circuit is disposed in th |
| 5859511 |
Motor with input-controlled high side driver |
January 12, 1999 |
| A circuit for operating a polyphase DC motor, such as the type having a plurality of "Y" connected stator coils, has circuitry for charging the coils at a rate which will reduce EMI and other noise, while maintaining an acceptable charge rate. The gate of a selected high side driving |
| 5856707 |
Vias and contact plugs with an aspect ratio lower than the aspect ratio of the structure in whic |
January 5, 1999 |
| A method of forming vias in an interlevel dielectric structure of an integrated circuit, such that the aspect ratio of the vias is smaller than the aspect ratios of vias having a height equal to the thickness of the entire interlevel dielectric structure, and the integrated circuit forme |
| 5856696 |
Field effect transistor having dielectrically isolated sources and drains |
January 5, 1999 |
| A field-effect transistor structure is described having a monocrystalline silicon channel region which is epitaxially continuous with an underlying monocrystalline silicon body region. Polycrystalline silicon source and drain regions abut the channel region. The source and drain regions |
| 5856233 |
Method of forming a field programmable device |
January 5, 1999 |
| A method is provided for forming a field programmable device of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first conductive layer is formed. A first, fusible, dielectric layer is formed over the first conductive layer. The dielectric |
| 5854539 |
Electroluminescent lamp driver circuit with signal tracking |
December 29, 1998 |
| An electroluminescent lamp is driven by a driving circuit that can supply an approximately sinusoidal signal, a bi-directional sawtooth signal or a single-ended sawtooth signal. Switches selectively transfer energy from a battery to an inductor and then from the inductor to the lamp. In |
| 5852359 |
Voltage regulator with load pole stabilization |
December 22, 1998 |
| A voltage regulator with load pole stabilization is disclosed. The voltage regulator consists of an error amplifier, an integrator which includes a switched capacitor, a pass transistor, and a feedback circuit. In one embodiment, the integrator circuit includes an amplifier, a capacitor, |
| 5850139 |
Load pole stabilized voltage regulator circuit |
December 15, 1998 |
| A voltage regulator with load pole stabilization is disclosed. An error amplifier has a non-inverting input receiving a reference voltage and an inverting input receiving a feedback voltage from the output of the voltage regulator. A gain stage has an input connected to the output of |
| 5848018 |
Memory-row selector having a test function |
December 8, 1998 |
| A memory-row selector includes an address input terminal, a mode terminal, and even-row-select and odd-row-select terminals. While a test signal level occupies the mode terminal (ie., during a test mode), the selector places either an active level or an inactive level on both of the |
| 5847465 |
Contacts for semiconductor devices |
December 8, 1998 |
| A method for fabrication of metal to semiconductor contacts results in sloped sidewalls in contact regions. An oxide layer is deposited and etched back to form sidewall spacers. A glass layer is then deposited and heated to reflow. After reflow, an etch back of the glass layer results is |
| 5847460 |
Submicron contacts and vias in an integrated circuit |
December 8, 1998 |
| A method is provided of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, an opening is formed partially through an insulating layer overlying |
| 5847457 |
Structure and method of forming vias |
December 8, 1998 |
| A method is provided for forming a contact opening or via of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first metal region is formed over an underlying region. A first insulating layer is formed over the integrated circuit. A second |
| 5845059 |
Data-input device for generating test signals on bit and bit-complement lines |
December 1, 1998 |
| A data input circuit is used in a memory device having an externally accessible data pin. The data input circuit includes first and second data output terminals and a test terminal that receives a test signal. A data converter is coupled to the first and second data output terminals and |
| 5841789 |
Apparatus for testing signal timing and programming delay |
November 24, 1998 |
| A method and apparatus for testing and programming signal timing are disclosed which can be incorporated into an integrated circuit device utilizing on-chip timed command signals and pulses. The method of the invention enables nonpermanent testing and retesting of a device at various |
| 5841784 |
Testing and repair of embedded memory |
November 24, 1998 |
| A method and circuits for coupling a memory embedded in an integrated circuit to interconnect pads during a memory test mode is disclosed. The integrated circuit contains a processor, an embedded memory and a switching circuit for: (1) temporary coupling the memory array and memory p |
| 5841709 |
Memory having and method for testing redundant memory cells |
November 24, 1998 |
| A memory device includes an array of matrix memory cells that each correspond to a matrix location within the matrix array, an array of redundant memory cells that each correspond to a redundant location within the redundant array, and address and test circuitry. During a first test |
| 5841195 |
Semiconductor contact via structure |
November 24, 1998 |
| A method is provided for forming contact via in an integrated circuit. Initially, a first buffer layer is formed over an insulating layer in an integrated circuit. The first buffer layer has a different etch rate from the insulating layer. A second buffer layer is then formed over the fi |
| 5837613 |
Enhanced planarization technique for an integrated circuit |
November 17, 1998 |
| A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass. |
| 5835427 |
Stress test mode |
November 10, 1998 |
| Accelerated failure of processing defects in an integrated circuit memory device is brought about by asserting all wordlines of the memory device to enable all passgates for a plurality of memory cells. Then all bitlines are pulled low to pull low all internal nodes of the plurality memo |
| 5834966 |
Integrated circuit sensing and digitally biasing the threshold voltage of transistors and relate |
November 10, 1998 |
| An integrated circuit includes a plurality of MOSFETs on a substrate. A plurality of sensing MOSFETs are used to generate a plurality of comparison signals based upon comparing signals related to the sensed initial threshold voltages to respective reference voltages from a spread of |
| 5834826 |
Protection against adverse parasitic effects in junction-isolated integrated circuits |
November 10, 1998 |
| A circuit, and method of operation, allows initial operation of a parasitic transistor in a junction isolated integrated circuit. The initial operation activates elements that produce a turn-on drive signal to a power transistor that has a part in the parasitic transistor, resulting in |
| 5834360 |
Method of forming an improved planar isolation structure in an integrated circuit |
November 10, 1998 |
| A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the substrate surface; the masking layer preferably comprising a nitride layer overlying a pad oxi |
| 5832596 |
Method of making multiple-bond shelf plastic package |
November 10, 1998 |
| A method for forming a package for an integrated circuit in which a plurality of conduction paths are formed on a first board and on a second board. Holes are formed in the first board and the second board wherein the holes are adapted for receiving pins. The holes are aligned and the |
| 5831897 |
SRAM memory cell design having complementary dual pass gates |
November 3, 1998 |
| A memory cell in which data is written and read from a pass gate. The memory cell has a connection to a first pass gate, connecting the memory cell to a bit line. Additionally, the memory cell has a second pass gate connecting the memory cell to a complementary bit line. The pass gates a |
| 5831457 |
Input buffer circuit immune to common mode power supply fluctuations |
November 3, 1998 |
| The present invention provides an input buffer circuit for reducing false transitions within a circuit. The input buffer circuit includes an input pad for receiving an input voltage, an input buffer having an input and a circuit for modifying a voltage entering the input buffer to track |
| 5831446 |
Process monitor test chip and methodology |
November 3, 1998 |
| A process monitor test chip and methodology allows process-related manufacturing defects to be quickly identified and isolated. A basic circuit block of a test chip having a number of inverter cells serially connected with a corresponding number of observation points before the input |
