| Patent Number |
Title Of Patent |
Date Issued |
| 5963025 |
Switching voltage regulator having a charge pump circuit |
October 5, 1999 |
| A voltage regulator (400) having a charge pump includes a bias current circuit (402) which produces a bias current (I.sub.bias). The bias current (I.sub.bias) is mirrored by a first mirror circuit (404) and multiplied by gain stage Q4.sub.beta and mirrored again by a factor "c" on the ou |
| 5960464 |
Memory sharing architecture for a decoding in a computer system |
September 28, 1999 |
| A method and apparatus employing a memory management system that can be used with applications requiring a large contiguous block of memory, such as video decompression techniques (e.g., MPEG 2 decoding). The system operates with a computer and the computer's operating system to request |
| 5960311 |
Method for forming controlled voids in interlevel dielectric |
September 28, 1999 |
| A method of forming a thick interlevel dielectric layer containing sealed voids, formed in a controlled manner, over a substantially planar surface in semiconductor device structure, and the semiconductor structure formed according to such a method. The sealed voids are used to reduce in |
| 5960277 |
Method of making a merged device with aligned trench FET and buried emitter patterns |
September 28, 1999 |
| A merged power device structure, of the emitter-switching type, in which the emitter of the bipolar power transistor has a minimum-width pattern which is aligned to the trenches of a trench control transistor. Thus the current density of the bipolar is maximized, since the emitter edge l |
| 5959910 |
Sense amplifier control of a memory device |
September 28, 1999 |
| A test mode of a memory device may be invoked that varies the sense amplifier clocking of the memory device as a function of manipulation of a control signal external to the memory device. At the appropriate logic state of a test mode enable signal, the test mode of the memory device is |
| 5956615 |
Method of forming a metal contact to landing pad structure in an integrated circuit |
September 21, 1999 |
| A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the fi |
| 5955915 |
Circuit for limiting the current in a power transistor |
September 21, 1999 |
| A current limiting circuit used with voltage regulators or other similar circuits is disclosed. The current limiting circuit uses two transistors, configured as a differential pair, combined with a fixed current source to limit the current available to a pass transistor of the voltage re |
| 5955770 |
Method of forming raised source/drain regions in an integrated circuit |
September 21, 1999 |
| A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of field oxide regions are formed overlying a substrate electrically isolating a plurality of transistors encapsulated in a |
| 5952858 |
Junction capacitor compensation for wave shaping |
September 14, 1999 |
| A method and structure for wave-shaping of digital waveforms of integrated circuit processes that do not have area efficient dielectric capacitors is disclosed. The dielectric capacitors of the prior art are replaced with a first, linearizing diode and a second diode of a wave-shaping ci |
| 5952707 |
Shallow trench isolation with thin nitride as gate dielectric |
September 14, 1999 |
| A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type disposed on a surface thereof and a dielectric layer including silicon nitride disposed on the surface. The dielectric layer includes openings at least p |
| 5951690 |
Synchronizing an audio-visual stream synchronized to a clock with a video display that is synchr |
September 14, 1999 |
| A DVD player that integrates a DVD device into a personal computer is provided. As such, the personal computer is able to output audio-visual works from a DVD CD-ROM. When integrating a DVD device with a personal computer, various problems must be overcome. For example, in a personal |
| 5950072 |
Low-profile removable ball-grid-array integrated circuit package |
September 7, 1999 |
| An integrated circuit package had leadless solderballs attached to the substrate with a conductive thermoplastic adhesive. The leadless solderballs are preferably made with a copper-nickel-gold alloy. The conductive thermoplastic is preferably of the silver fill type. The integrated |
| 5949720 |
Voltage clamping method and apparatus for dynamic random access memory devices |
September 7, 1999 |
| A circuit for clamping the voltage appearing on the bit lines of a dynamic random access memory (DRAM) device so that the voltage thereon is maintained above the low reference voltage source. The circuit includes pull-up devices connected to the bit lines of the DRAM device. The pull-up |
| 5949156 |
Precision capacitor ladder using differential equal-perimeter pairs |
September 7, 1999 |
| An integrated circuit capacitor ladder which uses a differential pair of capacitors for each step in the ladder. By pairing a square with a rectangle of equal perimeter, the contributions of edge and corner elements can be canceled out. This adds area and complexity, but greatly incr |
| 5946264 |
Method and structure for enhancing the access time of integrated circuit memory devices |
August 31, 1999 |
| A memory structure features a write driver circuit that is controlled to assist equilibrate devices recover one or more bitlines attached to a memory cell following the completion of a write operation of the memory cell. After the write operation, a write bus true and a write bus com |
| 5945818 |
Load pole stabilized voltage regulator circuit |
August 31, 1999 |
| A voltage regulator with load pole stabilization is disclosed. An error amplifier has a non-inverting input receiving a reference voltage and an inverting input receiving a feedback voltage from the output of the voltage regulator. A gain stage has an input connected to the output of |
| 5945738 |
Dual landing pad structure in an integrated circuit |
August 31, 1999 |
| A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A dual polysilicon landing pad is f |
| 5943598 |
Integrated circuit with planarized dielectric layer between successive polysilicon layers |
August 24, 1999 |
| A method of forming a portion of a semiconductor integrated circuit having a semiconductor substrate as well as the resulting integrated circuit. In the inventive method, various steps are involved. In one embodiment, for example, the method steps are as follows. First, there is formed a |
| 5942951 |
Method and apparatus for reducing a noise differential in an electronic circuit |
August 24, 1999 |
| In a high current, high frequency integrated circuit chip characteristic of producing an excess of internal on-chip circuit induced noise with respect to a low current, low frequency circuit implemented on the high current, high frequency integrated circuit chip, a method is disclosed fo |
| 5942798 |
Apparatus and method for automating the underfill of flip-chip devices |
August 24, 1999 |
| An apparatus and method for underfilling a silicon chip (16) to a substrate (12) by depositing an underfill dam (18) on the surface (20) of the substrate (12) prior to addition of the underfill material (14), is disclosed. A bead of underfill material (14) is provided on the substrate |
| 5940332 |
Programmed memory with improved speed and power consumption |
August 17, 1999 |
| A memory for storing a reorganizing array of an initial array of data of binary ones and zeros to enable decoding of the reorganized array to reproduce the information content of the initial array, and the method of reorganizing the initial array. The memory includes a data circuit array |
| 5939940 |
Low noise preamplifier for a magnetoresistive data transducer |
August 17, 1999 |
| A low noise preamplifier design which is configured such that the current through the first stage load resistor may be made relatively small in value making it possible to achieve a relatively large gain in the first stage thereby reducing the noise contribution of the load resistor and, |
| 5939934 |
Integrated circuit passively biasing transistor effective threshold voltage and related methods |
August 17, 1999 |
| An integrated circuit preferably includes a plurality of enhancement-mode MOSFETs on a substrate with each MOSFET having an initial threshold voltage, and a plurality of resistors connected to define a resistor voltage divider for passively biasing the MOSFETs to produce an absolute |
| 5939914 |
Synchronous test mode initialization |
August 17, 1999 |
| The entire data path of a synchronous integrated circuit device is initialized in a test mode upon power-up of the synchronous integrated circuit device. Upon power-up of the integrated circuit device in the test mode, a clock signal (either an external clock signal or an associated |
| 5939909 |
Driver circuit having preslewing circuitry for improved slew rate control |
August 17, 1999 |
| A driver circuit for a power device of a power driving stage is capable of providing slew rate control. The driver circuit includes the following elements: a charging source of current, a discharging source of current, a first switch, a second switch, a conductive device, a capacitive el |
| 5930673 |
Method for forming a metal contact |
July 27, 1999 |
| A method is provided for depositing aluminum thin film layers to form contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows improved surface migration of the deposited alumi |
| 5929695 |
Integrated circuit having selective bias of transistors for low voltage and low standby current |
July 27, 1999 |
| An integrated circuit includes a plurality of MOSFETs on a substrate. The plurality of MOSFETs preferably includes at least one MOSFET having a first conductivity type and at least one MOSFET having a second conductivity type. Each MOSFET has an initial threshold voltage. The integra |
| 5927992 |
Method of forming a dielectric in an integrated circuit |
July 27, 1999 |
| A method is provided for forming an improved device dielectric of a semiconductor integrated circuit, and an integrated circuit formed according to the same. For scaling geometries for use in the submicron regime, a composite dielectric layer used as a device dielectric is formed ove |
| 5926736 |
Low temperature aluminum reflow for multilevel metallization |
July 20, 1999 |
| The present invention provides a method for minimizing voids in a plug. The process begins by forming a conformal barrier layer within the hole and then forming a metal plug within the hole. Thereafter, a cap layer is formed over the metal plug in which the cap layer has a lower thermal |
| 5925910 |
DMOS transistors with schottky diode body structure |
July 20, 1999 |
| A DMOS device in a complex integrated circuit having a well region defined by a buried isolation region and an overlapping deep drain region within an epitaxial layer formed over a substrate, a body region having two source regions within the well region, insulated gates over the two sou |
| 5923133 |
Adaptive slew rate adjustment for a brushless multiphase DC motor and method |
July 13, 1999 |
| A set of circuits for controlling the slew rate of a driving transistor in a rotating three-phase DC motor having a "Y" configuration of coils. The slew rate is reduced when the rotational speed of the motor is low. The slew rate is controlled by controlling the voltage applied to a cont |
| 5920353 |
Multi-standard decompression and/or compression device |
July 6, 1999 |
| Circuits and methods for subdividing a decoder into functional blocks that can be accessed separately. The decoder includes a decoder module having a parser, a block decoder and a motion compensation engine, which can all be further subdivided into functional blocks. The functional block |
| 5920183 |
Voltage regulator for regulating its output voltage selectively with respect to more than one vo |
July 6, 1999 |
| A voltage regulator for producing an output voltage that selectively tracks a logic voltage or a reference voltage and method of operating the voltage regulator. The voltage regulator has a diode OR with a logic and reference transistors. The logic voltage is scaled to be close in value |
| 5920166 |
Control of slew rate during turn-on of motor driver transistors |
July 6, 1999 |
| A circuit for controlling the slew rate at a motor coil during turn-on in a commutation sequence is disclosed. The disclosed circuit includes a switched current mirror that receives the commutation signal, and that provides a mirrored current to the input of an integrating buffer amp |
| 5917353 |
Clock pulse extender mode for clocked memory devices having precharged data paths |
June 29, 1999 |
| According to the present invention, clock control logic circuitry of a clocked memory device using precharged data path techniques generates a self-timed pulse. The self-timed pulse is representative of a pulsed path active strobe or a reset strobe of the clocked memory device. The clock |
| 5917313 |
DC-to-DC converter with soft-start error amplifier and associated method |
June 29, 1999 |
| A DC-to-DC converter includes an error amplifier; a ramp generator for generating a ramp signal at the first input of the error amplifier independent of the output of the error amplifier and so that the output of the error amplifier ramps up at a relatively slow rate to avoid overshoot |
| 5917226 |
Integrated released beam, thermo-mechanical sensor for sensing temperature variations and associ |
June 29, 1999 |
| An integrated circuit and method are provided for sensing activity such as temperature variations in a surrounding environment. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to the switch detecting circui |
| 5917220 |
Integrated circuit with improved overvoltage protection |
June 29, 1999 |
| A special rail is provided along each edge of an integrated circuit chip with bias circuits connected to the ends of each special rail. The bias circuits charge the special rail to the V.sub.DD voltage level during normal operation, and clamp the special rail to the V.sub.SS rail upon th |
| 5914518 |
Method of forming a metal contact to landing pad structure in an integrated circuit |
June 22, 1999 |
| A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the fi |
| 5909636 |
Method of forming a landing pad structure in an integrated circuit |
June 1, 1999 |
| A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A dual polysilicon landing pad is f |
| 5905683 |
Method and structure for recovering smaller density memories from larger density memories |
May 18, 1999 |
| Therefore, according to the present invention, one or more bond pads of a memory device are connected to a corresponding address buffer or address buffers by a selection circuit which selectively allows the address buffer to ignore a signal on the bond pad. In order to define a smaller d |
| 5903054 |
Integrated circuit with improved pre-metal planarization |
May 11, 1999 |
| An integrated circuit wherein a planarization step has been performed before the primary metal deposition step, but after deposition of the adhesion and barrier layers. Thus the adhesion and barrier layers are present on the sidewalls of contact holes, but do not underlie the whole e |
| 5898329 |
Programmable pulse width modulation circuit |
April 27, 1999 |
| A circuit for producing multiple pulse width modulated outputs. The circuit includes a logic device for each pulse width modulated output. Each of the logic devices includes a first input, a second input, and a clock input, and each of logic device produces a logical high output in respo |
| 5898235 |
Integrated circuit with power dissipation control |
April 27, 1999 |
| An integrated circuit device such as an SRAM operating in a battery backup mode, or operating in a quiescent mode when deselected in the operation of a portable electronic device, includes a power dissipation control circuit that reduces the voltage on an internal power supply node so th |
| 5896336 |
Device and method for driving a conductive path with a signal |
April 20, 1999 |
| A signal driver receives an input signal and an enable signal, and generates an output signal from the input signal when the enable signal has an active state. When the enable signal has an inactive state, the signal driver draws substantially zero supply current regardless of the le |
| 5896040 |
Configurable probe pads to facilitate parallel testing of integrated circuit devices |
April 20, 1999 |
| Parallel testing of integrated circuit devices are facilitated such that it is not necessary that integrated circuit devices to be parallel tested be "ends only" devices. A side pad located along the sides, rather than the ends, of the integrated circuit device is electrically connected |
| 5896039 |
Configurable probe pads to facilitate parallel testing of integrated circuit devices |
April 20, 1999 |
| Parallel testing of integrated circuit devices are facilitated such that it is not necessary that integrated circuit devices to be parallel tested be "ends only" devices. A side pad located along the sides, rather than the ends, of the integrated circuit device is electrically connected |
| 5895237 |
Narrow isolation oxide process |
April 20, 1999 |
| A high performance CMOS process using grown field oxide for active area isolation takes advantage of process steps used in LDD transistor fabrication to reduce the chip space occupied by the field oxide. Portions of the spacer oxide layer are retained intact over the field oxide during |
| 5894160 |
Method of forming a landing pad structure in an integrated circuit |
April 13, 1999 |
| A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is |
| 5894158 |
Having halo regions integrated circuit device structure |
April 13, 1999 |
| A mask is used for lightly doped drain and halo implants in an integrated circuit device. The mask exposes only portions of the substrate adjacent to field effect transistor gate electrodes. Since the halo implant is made only near the transistor channels, where it performs a useful func |
