| Patent Number |
Title Of Patent |
Date Issued |
| 6180989 |
Selectively doped electrostatic discharge layer for an integrated circuit sensor |
January 30, 2001 |
| A structure and method for creating an integrated circuit passivation structure comprising, a circuit, a dielectric, and metal plates over which an insulating layer is disposed that electrically isolates the circuit, and a discharge layer that is deposited to form the passivation structu |
| 6180517 |
Method of forming submicron contacts and vias in an integrated circuit |
January 30, 2001 |
| A method is provided of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, an opening is formed partially through an insulating layer overlying |
| 6180509 |
Method for forming planarized multilevel metallization in an integrated circuit |
January 30, 2001 |
| A method is provided for forming planar multilevel metallization of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Multilevel metallization is achieved through a planar process at each layer to allow for minimum widths of lines and vias an |
| 6172548 |
Input stage with reduced transient time for use in multiplexing transducers that require a switc |
January 9, 2001 |
| The present application discloses an innovative improved circuit, in which the long transient at write-to-read transitions is avoided by using a shorting switch to short the inputs of the first amplifier stage together when the read amplifier is activated. This speeds up write-to-read |
| 6171879 |
Methods of forming thermo-mechanical sensor |
January 9, 2001 |
| An integrated circuit and method are provided for sensing activity such as temperature variations in a surrounding environment. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to the switch detecting circui |
| 6167544 |
Method and apparatus for testing dynamic random access memory |
December 26, 2000 |
| A method and apparatus for reducing the time for determining a memory refresh frequency for a dynamic random access memory. The method includes disabling the bootstrap circuitry associated with a word line when writing data into a memory cell during a test operation. For instances in whi |
| 6166869 |
Method and circuit for enabling rapid flux reversal in the coil of a write head associated with |
December 26, 2000 |
| An H-bridge for applying a current to a coil of a write head assembly for writing data to a magnetic media includes two pair of two switchable transistors. Each pair of transistors is connected between a supply voltage and a reference potential and is adapted to be connected to the c |
| 6163120 |
Simple back emf reconstruction in pulse width modulation (PWM) mode |
December 19, 2000 |
| A circuit and method for reconstructing the back emf of a floating coil of a polyphase dc motor in PWM mode is provided. The floating coil is coupled to a first capacitor through a floating phase switch that closes during a pulse produced by the PWM drive signaling the appropriate time t |
| 6159836 |
Method for forming programmable contact structure |
December 12, 2000 |
| A programmable semiconductor contact structure and method are provided. A semiconductor substrate has a first patterned conductive layer for forming an interconnect. A first insulating layer overlies the first patterned conductive layer. An opening is formed through the insulating layer |
| 6157578 |
Method and apparatus for accessing a memory device |
December 5, 2000 |
| A device and method for accessing a row of data in a semiconductor memory device in a single operation is disclosed. The device includes a row of latches having a width which matches the width of the memory array in the semiconductor memory device. The device includes precharge and e |
| 6153458 |
Method of forming a portion of a memory cell |
November 28, 2000 |
| The invention may be incorporated into a method for forming a vertically oriented semiconductor device structure, and the semiconductor structure formed thereby, by forming a first transistor over a portion of a substrate wherein the first transistor has a gate electrode and a source |
| 6147917 |
Apparatus and method for noise reduction in DRAM |
November 14, 2000 |
| An apparatus (and method) is provided that reduces noise in an embedded DRAM caused by noise in the Vdd supply. A circuit switches or decouples the bit line precharge voltage supply from the memory array to reduce noise in the memory array at time of bit line sensing. In addition, an |
| 6147899 |
Radiation hardened SRAM device having cross-coupled data cells |
November 14, 2000 |
| A memory cell with increased resistance to high energy particle radiation. When a memory cell is subjected to high energy particles hit, such as may occur in outer space or in certain harsh environments, design is provided that ensures the data will be maintained in its current state. In |
| 6145049 |
Method and apparatus for providing fast switching between floating point and multimedia instruct |
November 7, 2000 |
| A system and method is provided that adds another floating point register set in the floating point execution unit of a microprocessor. Thus, when the floating point state, or environment is stored as an image into memory, it is also stored as a copy in the additional internal registers. |
| 6144594 |
Test mode activation and data override |
November 7, 2000 |
| A memory device with a test mode control circuit for entering a test mode responsive to a high on the Vss pin or a low on the Vcc pin that supply power to the output pins during normal operation of the memory device. In test mode the wordlines and bitlines of the memory remain active fro |
| 6134125 |
AC and DC input power supply |
October 17, 2000 |
| An AC and DC input power supply includes an AC power supply circuit and an AC input for receiving a range of AC input voltages. A rectifier circuit is connected to the AC input. An isolation output transformer has first and second primary winding terminals and a low voltage winding secti |
| 6134060 |
Current bias, current sense for magneto-resistive preamplifier, preamplifying integrated circuit |
October 17, 2000 |
| A current bias, current sense magneto-resistive preamplifier for a hard disk drive and related methods preferably includes an MR sensor responsive to a current bias for sensing a change in magnetic data flux and responsively providing a change in electrical resistance. A preamplifying |
| 6133864 |
Analog-to-digital converter for processing analog signals from a large array of detectors |
October 17, 2000 |
| A parallel pipelined analog-to-digital converter for use with chips containing large arrays of detectors is described. In these A/D converters, the degree of parallelism decreases between earlier and later pipeline stages. That is, there are fewer instances of at least one of the lat |
| 6133107 |
Process for co-integrating DMOS transistors with schottky diode body structure |
October 17, 2000 |
| A DMOS device in a complex integrated circuit having a well region defined by a buried isolation region and an overlapping deep drain region within an epitaxial layer formed over a substrate, a body region having two source regions within the well region, insulated gates over the two sou |
| 6128243 |
Shadow memory for a SRAM and method |
October 3, 2000 |
| A method of operating a memory cell includes detecting a first power supply anomaly or condition. When the first power supply condition occurs, memory cell access to bit lines is disabled, a series of shadow memory access FETs within the memory cells are enabled and data from the memory |
| 6127868 |
Timer circuit |
October 3, 2000 |
| The a timer circuit and oscillator are disclosed. The timer circuit is similar in functionality to a '555 timer circuit but uses few transistors. The timer circuit has two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter. The two |
| 6124765 |
Integrated released beam oscillator and associated methods |
September 26, 2000 |
| An integrated oscillator and associated methods are provided for providing clock signals. The integrated oscillator preferably includes a micro-mechanical oscillating circuit for providing an oscillating clock signal. The micro-mechanical oscillating circuit preferably includes a sup |
| 6124751 |
Boost capacitor for an H-bridge integrated circuit motor controller having matching characterist |
September 26, 2000 |
| An H-bridge circuit having a boost capacitor coupled to the gate of the low-side driver. A driver, in the form of a switching transistor is connected between the load and ground, thus providing a low-side driver. A capacitor is coupled to the gate of the low-side driver to provide a |
| 6121678 |
Wrap-around interconnect for fine pitch ball grid array |
September 19, 2000 |
| An apparatus and method for producing a wrap-around interconnect substrate (60) comprising a substrate (42) having semi-circular vias (62) having openings (64) created by separating through cylindrical vias (62) that were positioned along cutting lines (46a, 46b) that formed part of an |
| 6118717 |
Method and apparatus for loading directly onto bit lines in a dynamic random access memory |
September 12, 2000 |
| A device for directly loading data onto bit lines of DRAMs. The device eliminates the need for performing a read cycle prior to a write cycle by bypassing the sense amplifiers of the DRAM. An I/O data line is connected to a bit line by a first transmission gate. A second transmission gat |
| 6118602 |
Preamplifier for a read/write head |
September 12, 2000 |
| A multi-head, disc drive, of a data storage system having a preamplifier that is split into a mother chip and set of daughter chips, each daughter chip corresponding to a head in the disc drive. The daughter chips contain very little circuitry, typically just a write driver, the front en |
| 6118188 |
Apparatus and method for switching between two power supplies of an integrated circuit |
September 12, 2000 |
| A power supply switching circuit employs hysteresis to ensure stable, timely, and accurate transition between a primary power source and a secondary power source of an integrated circuit. A comparison element of the circuit compares a first voltage signal derived from a primary voltage |
| 6114862 |
Capacitive distance sensor |
September 5, 2000 |
| A distance sensor has a capacitive element in turn having a first capacitor plate which is positioned facing a second capacitor plate whose distance is to be measured. In the case of fingerprinting, the second capacitor plate is defined directly by the skin surface of the finger being pr |
| 6114745 |
Bipolar transistor having high emitter efficiency |
September 5, 2000 |
| A vertical conduction NPN bipolar transistor with a tunneling barrier of silicon carbide in the emitter providing a high emitter injection efficiency and high, stable current gain. The emitter structure comprises a heavily doped polysilicon layer atop a silicon carbide layer that con |
| 6113399 |
Low-profile socketed packaging system with land-grid array and thermally conductive slug |
September 5, 2000 |
| A socketed integrated circuit packaging system, including a packaged integrated circuit and a socket therefor, is disclosed. The integrated circuit package includes a device circuit board to which a thermally conductive slug is mounted; the underside of the device circuit board has a |
| 6111801 |
Technique for testing wordline and related circuitry of a memory array |
August 29, 2000 |
| A technique for testing wordline and related circuitry of a memory array is disclosed. The memory array includes a plurality of memory cells arranged in a plurality of rows, wherein each of the plurality of rows has a respective wordline connected to respective ones of the plurality of |
| 6111319 |
Method of forming submicron contacts and vias in an integrated circuit |
August 29, 2000 |
| A method is provided of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, an opening is formed partially through an insulating layer overlying |
| 6110791 |
Method of making a semiconductor variable capacitor |
August 29, 2000 |
| A variable capacitor in a semiconductor device is described in which the capacitance is varied by the movement of a dielectric material in the space between the plates of the capacitor in response to an external stimulus. A method of making such a variable capacitor is also described |
| 6108455 |
Non-linear image filter for filtering noise |
August 22, 2000 |
| A system and method for reducing noise using recursive noise level estimation. The system and method for noise reduction substitute a target pixel in a processing window with a weighted average of a plurality of neighboring pixels according to the degree of similarity between thc tar |
| 6107865 |
VSS switching scheme for battery backed-up semiconductor devices |
August 22, 2000 |
| A battery backed-up semiconductor device employs a Vss switching configuration to provide uninterrupted battery power to critical circuitry of the device even in the event of external conditions, such as undershoot, that threaten to corrupt data stored by the device. Both primary pow |
| 6107194 |
Method of fabricating an integrated circuit |
August 22, 2000 |
| The present invention provides improved device speed by using two silicides with two different compositions: one silicide is overlaid on a polysilicon gate layer, to form a "polycide" layer with improved sheet resistance, and the other is clad on at least some "active" areas of the monoc |
| 6104416 |
Tiling in picture memory mapping to minimize memory bandwidth in compression and decompression o |
August 15, 2000 |
| A method of storing a picture in a memory such that the latency of the memory can be reduced when retrieving a picture from the memory to be displayed while still reducing the bandwidth when retrieving an array portion of the picture from the memory, and a memory architecture. The me |
| 6101618 |
Method and device for acquiring redundancy information from a packaged memory chip |
August 8, 2000 |
| A method and circuit for testing a packaged semiconductor memory device allow the acquisition of information on redundant elements by performing one of three possible redundancy rollcall tests on the packaged memory chip. By stimulating the packaged device's pins, the memory chip is set |
| 6101568 |
Bus interface unit having dual purpose transaction buffer |
August 8, 2000 |
| A bus interface unit includes a random-access transaction buffer and at least one pointer queue. The transaction buffer stores entries for both in-order transactions and combinable write transactions, and the pointer queue stores pointers to the buffer entries for in-order transactions s |
| 6100194 |
Silver metallization by damascene method |
August 8, 2000 |
| Silver interconnects are formed by etching deep grooves into an insulating layer over the contact regions, exposing portions of the contact regions and defining the interconnects. The grooves are etched with a truncated V- or U-shape, wider at the top than at any other vertical location, |
| 6096634 |
Method of patterning a submicron semiconductor layer |
August 1, 2000 |
| A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. An interlevel dielectric layer is formed over the surface of the integrated circuit. A planarizing layer is formed over the interlevel |
| 6094026 |
Overtemperature warning cycle in operation of polyphase DC motors |
July 25, 2000 |
| A method and integrated circuit for providing drive signals to a polyphase dc motor. The integrated circuit is fabricated on a semiconductor substrate for providing drive signals to a polyphase dc motor. The circuit includes a coil drive circuit for connection to drive coils of the motor |
| 6093963 |
Dual landing pad structure including dielectric pocket |
July 25, 2000 |
| A dual landing pad structure is formed with a dielectric pocket. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provid |
| 6091794 |
Fast synchronous counter |
July 18, 2000 |
| A synchronous counter circuit having a plurality of bit counting stages, each corresponding to a bit position for representing counts, from a least significant bit to a most significant bit. Each bit counting stage includes a flip-flip circuit and a synchronization circuit and each i |
| 6091630 |
Radiation hardened semiconductor memory |
July 18, 2000 |
| A radiation hardened memory device having static random access memory cells includes active gate isolation structures placed in series with oxide isolation regions between the active regions of a memory cell array. The active gate isolation structure includes a gate oxide and polycrystal |
| 6091222 |
Statistical phase detection and go start-up algorithm |
July 18, 2000 |
| A method for starting a polyphase DC motor having a rotor. The position of the rotor is detected by initiating current in each of the phases of the motor and measuring a time period between the initiation of current in the coil and an instant when the current exceeds a threshold current. |
| 6091132 |
Passivation for integrated circuit sensors |
July 18, 2000 |
| A structure and method for creating an integrated circuit passivation comprising, a circuit (16) over which an insulating layer (26 and/or 28) is disposed that electrically and hermetically isolates the circuit (16) and a silicon carbide layer (30) to form a passivation (24) to protect a |
| 6091082 |
Electrostatic discharge protection for integrated circuit sensor passivation |
July 18, 2000 |
| A structure and method for creating an integrated circuit passivation (24) comprising, a circuit (16), a dielectric (18), and metal plates (20) over which an insulating layer (26) is disposed that electrically and hermetically isolates the circuit (16), and a discharge layer (32) that is |
| 6088256 |
Integrated circuit with electrically programmable fuse resistor |
July 11, 2000 |
| Composite layers of titanium silicide and polysilicon define a fuse resistor within a programmable fuse element that increases its resistance from about 50 ohms in the unprogrammed state to about 250 K-ohms in the programmed state by creating a discontinuity in the silicide layer imm |
| 6087709 |
Method of forming an integrated circuit having spacer after shallow trench fill and integrated c |
July 11, 2000 |
| A method of forming an isolation region in an integrated circuit and an integrated circuit formed thereby. A method preferably includes forming at least one trench in a semiconductor substrate, forming an insulation layer of material in the at least one trench and on peripheral regions o |
