| Patent Number |
Title Of Patent |
Date Issued |
| 6356962 |
Network device and method of controlling flow of data arranged in frames in a data-based network |
March 12, 2002 |
| A method and network device are disclosed using a look-ahead watermark in a FIFO memory. In accordance with the present invention, a watermark interrupt is generated from a FIFO memory when data in the FIFO memory has crossed a watermark threshold. A data burst is transferred through a |
| 6355979 |
Hard mask for copper plasma etch |
March 12, 2002 |
| A hard mask, e.g., a silicon dioxide or silicon nitride film, is used to avoid organic polymer materials in copper plasma etch applications. The hard mask would be deposited as a blanket layer on the Cu metal layer and itself be patterned and etched with a conventional photolithographic |
| 6350684 |
Graded/stepped silicide process to improve MOS transistor |
February 26, 2002 |
| A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to redu |
| 6347381 |
Test mode circuitry for electronic storage devices and the like |
February 12, 2002 |
| A detection circuit and a test mode circuit incorporating the detection circuit is disclosed. The detection circuit includes an N-channel transistor having a first source, a first gate, and a first drain, wherein the first drain is connected to a supply voltage. The detection circuit |
| 6347161 |
Non-linear image filter for filtering noise |
February 12, 2002 |
| A system and method for reducing noise using recursive noise level estimation. The system and method for noise reduction substitute a target pixel in a processing window with a weighted average of a plurality of neighboring pixels according to the degree of similarity between the tar |
| 6346739 |
Static charge dissipation pads for sensors |
February 12, 2002 |
| A structure and method for dissipating charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry, and a conductive path and passivation layers disposed over the underlying dielectric layer wherein the conductive pad forms an electrically con |
| 6343364 |
Method and device for local clock generation using universal serial bus downstream received sign |
January 29, 2002 |
| A method and device is disclosed for generating a local clock signal CLK1X (172) from Universal Synchronous Bus downstream-received differential signals DM and DP carrying the downstream received bit-serial signal. The method and device does not require the use of a crystal or resonator. |
| 6343024 |
Self-adjustable impedance line driver with hybrid |
January 29, 2002 |
| A pair of equivalent controlled impedance buffers are connected in a push-pull configuration to a transformer primary coil. A pair of equivalent pre-drivers are connected to the pair of buffers. Each pre-driver receives a driver input signal and outputs a buffer input signal (based o |
| 6339028 |
Vacuum loadlock ultra violet bake for plasma etch |
January 15, 2002 |
| An improved vacuum plasma etching device for plasma etching semiconductor wafers that have a photo-resist pattern. The improved plasma etching device has a reaction chamber in which the plasma etching is performed during a process cycle, an entrance vacuum loadlock for holding the next |
| 6330145 |
Apparatus and method for contacting a sensor conductive layer |
December 11, 2001 |
| A structure and method is disclosed for grounding an electrostatic discharge device of an integrated circuit to dissipate electrostatic charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry and a conductive layer disposed over the underl |
| 6329941 |
Digital-to-analog converting device and method |
December 11, 2001 |
| A digital-to-analog converter (DAC) having a first sub-DAC for generating a coarse current level based upon the most significant bits of the digital input signal, and a second sub-DAC for generating a fine current level in response to the least significant bits of the digital input signa |
| 6327615 |
Method and system of controlling transfer of data by updating descriptors in descriptor rings |
December 4, 2001 |
| A method and system of controlling the transfer of data arranged in frames between a host and network device, such as an HDLC controller, having a shared system memory is disclosed. A frame is received within frame data buffers of the shared system memory. A single frame can span more th |
| 6326689 |
Backside contact for touchchip |
December 4, 2001 |
| A contact is formed within an active region of a substrate at the edge of a die, preferably within the first metallization level in the active region of the substrate. An opening having sloped sidewalls is then etched into the back side of the substrate, exposing a portion of the active |
| 6326647 |
Packaging and mounting of spherical semiconductor devices |
December 4, 2001 |
| A spherical semiconductor device that includes at least one circuit element and at least one power pad connecting the circuit element to a supply voltage. The circuit element can communicate with at least one external device through at least one input/output interface. In a preferred |
| 6326227 |
Topographical electrostatic protection grid for sensors |
December 4, 2001 |
| A structure and method for dissipating charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry a gap being formed conformally between adjacent plates and a topographic discharge grid over the underlying dielectric layer and wherein the top |
| 6324633 |
Division of memory into non-binary sized cache and non-cache areas |
November 27, 2001 |
| A cache system and method for configuring and accessing a cache that enables a binary-sized memory space to be efficiently shared amongst cache and non-cache uses. A storage device is provided having a plurality of blocks where each block is identified with a block address. An access |
| 6324225 |
Timing recovery for data sampling of a detector |
November 27, 2001 |
| A partial response Class 4 detector in a recording and retrieval system and method of operating the detector for correcting the timing error of the detector. The detector includes a sequence table and comparison circuitry for comparing a sequence of data samples that includes previous an |
| 6323609 |
Alternate high-side/low-side PWM operation of brushless motors |
November 27, 2001 |
| A brushless DC motor system in which PWM current control is performed by chopping the high-side driver during one half of a single cycle, and chopping the low-side driver during one half of a single cycle. |
| 6320473 |
Integrated oscillator circuit apparatus with capacitive coupling for reducing start-up voltage |
November 20, 2001 |
| The present invention relates to oscillator circuits for providing periodic signals. The oscillator circuit includes a crystal element having a high Q value and good stability. A high-gain amplifier is used with the crystal element to produce an oscillating signal. The oscillator is furt |
| 6317764 |
Apparatus for computing transcendental functions quickly |
November 13, 2001 |
| The invention provides a method and system for computing transcendental functions quickly: (1) the multiply ALU is enhanced to add a term to the product, (2) rounding operations for intermediate multiplies are skipped, and (3) the Taylor series is separated into two partial series which |
| 6317508 |
Scanning capacitive semiconductor fingerprint detector |
November 13, 2001 |
| A scanning fingerprint detection system that includes an array of capacitive sensing elements. The array has a first dimension greater than the width of a fingerprint and a second dimension less than the length of a fingerprint. Each of the capacitive sensing elements has a size less |
| 6310927 |
First order tuning circuit for a phase-locked loop |
October 30, 2001 |
| A first order phase-locked loop includes a tuning circuit which allows phase lock to be quickly reached, and to be maintained during transient situations such as loss of the data signal. Such an improved circuit has a tuning circuit for the voltage controlled oscillator which utilizes tw |
| 6310485 |
Integrated circuit device having a burn-in mode for which entry into and exit from can be contro |
October 30, 2001 |
| An integrated circuit structure and method provides a burn-in stress test mode that facilitates stress testing of an integrated circuit device in a burn-in oven. The integrated circuit structure and method is capable of disabling a time-out feature of an IC memory device during a stress |
| 6307835 |
Method and apparatus for controlling data flow in data communication networks |
October 23, 2001 |
| A method and apparatus for controlling data flow of data communications in a network are provided. A method preferably includes dynamically varying a minimum frame slot number, transmitting at least bytes of data from a frame of data of a slot, and determining the end of the frame of dat |
| 6307699 |
Bimodal biasing of magneto resistive heads |
October 23, 2001 |
| A system and method for selecting between two biasing modes for biasing magneto resistive heads in a disk drive. A mode selector selects either a voltage biasing circuit or a current biasing circuit to supply the bias voltage or bias current, respectively, to a magneto resistive head. Th |
| 6307415 |
Hysteresis circuit |
October 23, 2001 |
| The a timer circuit and oscillator are disclosed. The timer circuit is similar in functionality to a '555 timer circuit but uses few transistors. The timer circuit has two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter. The two |
| 6303452 |
Method for making transistor spacer etch pinpoint structure |
October 16, 2001 |
| A method is provided for forming a transistor spacer etch endpoint structure of an integrated circuit, and an integrated circuit formed according to the same. A gate is formed over a portion of a substrate. A dielectric layer is formed over the integrated circuit and an oxide layer i |
| 6300670 |
Backside bus vias |
October 9, 2001 |
| Metal taps for bus conductors are formed within an active layer, within one or more of the metallization levels, on the active side of a substrate in the area of a bus via. Alignment marks are formed in the same metallization level, in the same area. A slot is then blind etched from |
| 6298369 |
High speed multiplier |
October 2, 2001 |
| The high speed multiplier takes advantage of results from previous calculations by recognizing that in many cases the multiplicand between a first and second multiplication differs only slightly. Thus, the present system divides the multiplicand into a cache lookup bit (CLB) and a table |
| 6297996 |
Test mode activation and data override |
October 2, 2001 |
| A memory device with a test mode control circuit for entering a test mode responsive to a high on the Vss pin or a low on the Vcc pin that supply power to the output pins during normal operation of the memory device. In test mode the wordlines and bitlines of the memory remain active fro |
| 6297919 |
Write head with switchable impedance and method for operating same |
October 2, 2001 |
| A write head is described having a switchable damping resistance coupled in parallel with an inductor. The damping resistance is decoupled from the inductor by rendering a transistor nonconductive when a direction of current in the inductor changes. The damping resistance is then coupled |
| 6297698 |
Circuit for automatic regulation of a differential amplifier's gain |
October 2, 2001 |
| A circuit for regulating the gain of a variable differential gain amplifier. In one embodiment, a fully differential amplifier amplifies the outputs of the variable gain amplifier. The outputs of the fully differential amplifier are applied to a three input comparator so that if eith |
| 6297603 |
Circuit and method to avoid high current spikes in stator windings |
October 2, 2001 |
| A circuit for minimizing the current spikes in through the stator coils in a brushless dc motor is disclosed. The circuit includes a voltage amplifier for receiving an input signal voltage and a feedback voltage, a compensation circuit for compensating the output of the voltage amplifier |
| 6297110 |
Method of forming a contact in an integrated circuit |
October 2, 2001 |
| A method is provided for forming an improved contact opening of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Planarization of the semiconductor structure is maximized and misalignment of contact openings is tolerated by first forming a c |
| 6295224 |
Circuit and method of fabricating a memory cell for a static random access memory |
September 25, 2001 |
| A circuit and method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic |
| 6294939 |
Device and method for data input buffering |
September 25, 2001 |
| A substantially noise-free data input buffer for an asynchronous device, such as a static random access memory (SRAM). The input buffer generates either a logical true or complement output signal representation of a data input signal and includes timing circuitry to delay an edge transit |
| 6292383 |
Redundant memory cell for dynamic random access memories having twisted bit line architectures |
September 18, 2001 |
| A dynamic random access memory (DRAM) device is disclosed. The DRAM device includes a memory cell array having a twisted bit line architecture. The memory cell array includes at least one pair of redundant rows of memory cells. Redundant row decode circuitry is capable of configuring the |
| 6291845 |
Fully-dielectric-isolated FET technology |
September 18, 2001 |
| A field-effect transistor structure wherein a single patterned thin film semiconductor layer: is monocrystalline, and epitaxially matched to and dielectrically isolated from an underlying body region, in channel locations; and is polycrystalline in source/drain locations which abut s |
| 6291344 |
Integrated circuit with improved contact barrier |
September 18, 2001 |
| Methods of forming, in an integrated circuit, aluminum-silicon contacts with a barrier layer is disclosed. The barrier layer is enhanced by the provision of titanium oxynitride layers adjacent the silicide film formed at the exposed silicon at the bottom of the contact. The titanium |
| 6291337 |
Elimination of cracks generated after a rapid thermal process step of a semiconductor wafer |
September 18, 2001 |
| Two improved process steps of eliminating cracks within TiN and/or BPSG layers after the RTP process are provided. The first is to provide a low deposition power, preferably below 6.5 KWH, and a high process pressure, preferably above 5.6 mTorr, to the TiN layer. No crack is found for th |
| 6288521 |
Intelligent power management for rechargeable batteries |
September 11, 2001 |
| An electronic device battery pack for a battery requiring cycling to prolong lifetime is divided into at least two parallel cells for which the charging state is automatically maintained. When external power is available and one or more cells is substantially discharged, the substant |
| 6287963 |
Method for forming a metal contact |
September 11, 2001 |
| A method is provided for depositing aluminum thin film layers to form contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows surface migration of the deposited aluminum atoms |
| 6285801 |
Non-linear adaptive image filter for filtering noise such as blocking artifacts |
September 4, 2001 |
| A filter reduces artifacts, such as grid noise and staircase noise, in block-coded digital images with image block boundaries. The type of filtering is determined after an estimation of the image global metrics and local metrics. For areas of the image near grid noise, the filter per |
| 6284584 |
Method of masking for periphery salicidation of active regions |
September 4, 2001 |
| An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells. |
| 6281734 |
Reference voltage adjustment |
August 28, 2001 |
| A reference voltage trim circuit includes a voltage follower receiving the reference voltage to be trimmed, with one or more resistive loads providing predefined voltage shifts serially connected between the output of the voltage follower and the output of the trim circuit. The voltage |
| 6278337 |
Integrated released beam oscillator and associated methods |
August 21, 2001 |
| An integrated oscillator and associated methods are provided for providing clock signals. The integrated oscillator preferably includes a micro-mechanical oscillating circuit for providing an oscillating clock signal. The micro-mechanical oscillating circuit preferably includes a sup |
| 6275078 |
Self-adjustable impendance line driver |
August 14, 2001 |
| A pair of equivalent controlled impedance buffers are connected in a push-pull configuration to a transformer primary coil. A pair of equivalent pre-drivers are connected to the pair of buffers. Each pre-driver receives a driver input signal and outputs a buffer input signal and a pr |
| 6271137 |
Method of producing an aluminum stacked contact/via for multilayer |
August 7, 2001 |
| A method is provided for forming improved quality interlevel aluminum contacts in semiconductor integrated circuits. A contact opening is formed through an insulating layer. A barrier layer is deposited over the surface of the integrated circuit. An aluminum layer is then deposited at |
| 6271063 |
Method of making an SRAM cell and structure |
August 7, 2001 |
| A six transistor static random access memory (SRAM) cell with thin-film pull-up transistors and method of making the same includes providing two bulk silicon pull-down transistors of a first conductivity type, two active gated pull-up thin-film transistors (TFTs) of a second conductivity |
| 6265312 |
Method for depositing an integrated circuit tungsten film stack that includes a post-nucleation |
July 24, 2001 |
| A tungsten film stack is formed on a wafer using a deposition chamber by first depositing a nucleation on the wafer in the presence of a carrier gas, such as nitrogen. Following deposition of the nucleation, excess carrier gas is evacuated from the deposition chamber. Then, following |
