| Patent Number |
Title Of Patent |
Date Issued |
| RE40282 |
Edge transition detection circuitry for use with test mode operation of an integrated circuit me |
April 29, 2008 |
| An integrated circuit structure and method provides for an integrated circuit device to respond to an edge transition detection (ETD) pulse in one of two ways. First, in response to the ETD pulse, the integrated circuit device exits a test mode at least temporarily every cycle of the |
| RE39918 |
Direct current sum bandgap voltage comparator |
November 13, 2007 |
| A direct current sum bandgap voltage comparator for detecting voltage changes in a power supply. The direct current sum bandgap voltage comparator includes a summing node, current sources connected to the summing node and the power supply, and an indicator circuit connected to the su |
| RE39690 |
Enhanced planarization technique for an integrated circuit |
June 12, 2007 |
| A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass. |
| RE38891 |
Programmable load transient compensator for reducing the transient response time to a load capab |
November 22, 2005 |
| A load transient compensator and method of operating the load transient compensator for reducing the transient response time to a load .[.capable of operating at either of several consumption levels when the load changes its power consumption level.]. . The load transient compensator has |
| RE38250 |
Bandgap reference circuit |
September 16, 2003 |
| According to the present invention, a circuit, utilizing a minimum number of bipolar devices and current mirror scaling devices, generates a bandgap reference voltage. The bandgap voltage generated by the bandgap reference circuit is a function of a plurality of sized current mirror devi |
| RE38045 |
Data compensation/resynchronization circuit for phase lock loops |
March 25, 2003 |
| A circuit that compensates for delays induced by clock generation logic and distributed clock drivers in phase lock loop applications is disclosed. The circuit is a phase lock loop (PLL) which contains a clock synchronization circuit that operates to synchronize a transition edge of |
| RE37876 |
Power supply switch reference circuitry |
October 15, 2002 |
| An apparatus and method for switching between two power supplies, a primary power supply and a secondary power supply. The present invention generates a first reference voltage using the voltage of the primary power supply and the secondary power supply, wherein the primary power supply |
| RE37769 |
Methods for fabricating memory cells and load elements |
June 25, 2002 |
| A contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the |
| RE37708 |
Programmable bandwidth voltage regulator |
May 21, 2002 |
| A method for reducing the transient response time of a voltage regulator when the load attached to it is entering or exiting a lower power consumption level by changing the bandwidth of the voltage regulator without compromising its stability, and a bandwidth regulator for implementi |
| RE37082 |
RF transistor package with nickel oxide barrier |
March 6, 2001 |
| An improved transistor package with superior stability to wave soldering, having a nickel oxide barrier strip formed on the surface of the leads. |
| RE36938 |
Method of forming a landing pad structure in an integrated circuit |
October 31, 2000 |
| A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is |
| RE36319 |
Structure for deselective broken select lines in memory arrays |
September 28, 1999 |
| According to the present invention, a structure for holding broken select lines in a memory array deselected addresses the prior art problems associated with floating broken select lines, such as standby current and disruption of attached memory cells. The structure is a high impedance |
| RE36292 |
Operational analysis device of the scan path type having a single scanning clock and a single ou |
September 7, 1999 |
| The device comprises a first chain of scanning cells located at the stimulation input of each respective functional block of the integrated circuit and a second chain of scanning cells located at the assessment output of each respective functional block of the integrated circuit. Each |
| 7413129 |
USB device with secondary USB on-the-go function |
August 19, 2008 |
| A USB device includes first and second communications ports and a processor operable for configuring the first communications port for connecting to a USB host and configuring the second communications port as a USB master connecting to a USB slave device. The processor can be formed |
| 7412369 |
System and method for designing and optimizing the memory of an embedded processing system |
August 12, 2008 |
| There is disclosed an apparatus for designing and optimizing a memory for use in an embedded processing system. The apparatus comprises: 1) a simulation controller for simulating execution of a test program to be executed by the embedded processing system; 2) a memory access monitor |
| 7411433 |
Reset ramp control |
August 12, 2008 |
| A reset ramp control structure and method is described. A fast ramp down condition of a monitored voltage is detected and used to force the state of system reset. Delay between fast ramp detection and the forcing of system reset is adjustable. Operation is adaptable to include all DC |
| 7405740 |
Context sensitive scaling device and method |
July 29, 2008 |
| A method is provided for scaling a source image to produce a destination image. According to the method, a local context metric is calculated from a local portion of the source image. A convolution kernel is generated from a plurality of available convolution kernels based on the calcula |
| 7402454 |
Molded integrated circuit package with exposed active area |
July 22, 2008 |
| An integrated circuit die having an active area that must remain exposed after packaging is secured by a compliant die attachment by which the integrated circuit die is held in position within a transfer mold during encapsulation. The compliant die attachment may comprise a flexible, |
| 7398066 |
Communication system control using reliability data |
July 8, 2008 |
| A method and apparatus for recovering a data symbol from a communication signal in which the communication signal is processed to produce a baseband waveform that is then sampled to obtain a channel sequence. The channel sequence is decoded to obtain an estimate of the data symbol to |
| 7397097 |
Integrated released beam layer structure fabricated in trenches and manufacturing method thereof |
July 8, 2008 |
| A released beam structure fabricated in trench and manufacturing method thereof are provided herein. One embodiment of a released beam structure according to the present invention comprises a semiconductor substrate, a trench, a first conducting layer, and a beam. The trench extends into |
| 7389013 |
Method and system for vertical optical coupling on semiconductor substrate |
June 17, 2008 |
| Connection between optical fibers and optical components within a semiconductor substrate. A lens is created at the front of a semiconductor substrate. A tapered hole is created in the back of the substrate exposing part or all of the surface of the lens. An optical component is form |
| 7386581 |
Performance FIR filter |
June 10, 2008 |
| A single bit FIR filter that minimizes computation time by pre-storing outputs or portions of outputs for accumulation and output. |
| 7385433 |
Analog switch with reduced parasitic bipolar transistor injection |
June 10, 2008 |
| According to the invention a well-switching arrangement, with a semiconductor circuit including a switch having an input terminal, an output terminal and a body region and at least one comparator having a first input coupled to at least one of the terminals and a second input coupled |
| 7382848 |
First order tuning circuit for a phase-locked loop |
June 3, 2008 |
| A first order phase-locked loop includes a tuning circuit which allows phase lock to be quickly reached, and to be maintained during transient situations such as loss of the data signal. Such an improved circuit has a tuning circuit for the voltage controlled oscillator which utilizes tw |
| 7382568 |
Circuit and method for detecting a servo wedge on spin-up of a data-storage disk |
June 3, 2008 |
| A servo circuit includes a servo channel and a processor. The servo channel recovers servo data from servo wedges that identify respective data sectors on a data-storage disk. The processor detects one of the servo wedges on spin up of the disk, i.e., while the disk is attaining or a |
| 7375909 |
Write driver with power optimization and interconnect impedance matching |
May 20, 2008 |
| A write driver for driving a write current through a write head connected to the write head by an interconnect or flexible transmission line. The write driver includes a circuit matching an output impedance of the write driver to the odd characteristic impedance of the interconnect and |
| 7373522 |
Smart card with enhanced security features and related system, integrated circuit, and methods |
May 13, 2008 |
| An integrated circuit (IC) may include at least one smart card memory for storing a set of default requests and at least one alternate request for each default request. The IC may further include a microprocessor connected to the at least one smart card memory for communicating with a |
| 7372728 |
Magnetic random access memory array having bit/word lines for shared write select and read opera |
May 13, 2008 |
| A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row |
| 7372304 |
System and method for glitch detection in a secure microcontroller |
May 13, 2008 |
| An apparatus includes a plurality of macrocells formed from logic capable of performing one or more functions. The apparatus also includes a clock tree capable of receiving a clock signal and providing at least one copy of the clock signal to each macrocell. The clock tree includes a loc |
| 7372290 |
System and method for using dummy cycles to mask operations in a secure microcontroller |
May 13, 2008 |
| A secure device includes a memory capable of storing information. The secure device also includes a secure microcontroller capable of securing the information in the memory. The secure microcontroller includes a plurality of registers. The secure microcontroller also includes combina |
| 7372160 |
Barrier film deposition over metal for reduction in metal dishing after CMP |
May 13, 2008 |
| A protective barrier layer, formed of a material such as titanium or titanium nitride for which removal by chemical mechanical polishing (CMP) is primarily mechanical rather than primarily chemical, formed on a conformal tungsten layer. During subsequent CMP to pattern the tungsten l |
| 7370301 |
Method and apparatus for mixing static logic with domino logic |
May 6, 2008 |
| An automatic method for assigning the clock phases on a domino datapath embedding static gates includes replacing domino cells on non-critical paths by a static equivalent cell, delaying the clock arrival on domino gates driven by static signals, ensuring that critical data never waits |
| 7370264 |
H-matrix for error correcting circuitry |
May 6, 2008 |
| A matrix H for encoding data words is defined for wide word ECC with uniform density and a reduced number of components. The H-matrix is incorporated in an encode unit operable to Hamming encode a data word with a 10.times.528 matrix generated in groups of four columns wherein; a fir |
| 7370136 |
Efficient and flexible sequencing of data processing units extending VLIW architecture |
May 6, 2008 |
| A very long instruction word processor with sequence control. During each cycle the processor generates control signals to functional units based on the values in fields of an instruction. Each instruction may include an iteration count specifying the number of cycles for which the contr |
| 7369982 |
Multi-mode smart card emulator and related methods |
May 6, 2008 |
| An emulator for a multi-mode smart card may include emulation circuitry for performing smart card applications in a plurality of operational modes. The emulator may also include a smart card connector to be connected to a smart card adapter operable in at least one of the plurality o |
| 7369577 |
Code group acquisition procedure for a UMTS-FDD receiver |
May 6, 2008 |
| Step 2 demodulation is conventionally performed using a secondary synchronization channel that correlates a received signal at a known time slot location against each of a plurality of sequences associated with the secondary synchronization code. The disclosed implementation proposes |
| 7368947 |
Voltage translating control structure |
May 6, 2008 |
| A voltage translating control structure for switching logic is described. A battery drain problem is corrected by this structure. The voltage translating feature allows reliable switching between power supply and battery even if the power supply voltage has significantly decreased. O |
| 7366932 |
Method and apparatus to adapt the clock rate of a programmable coprocessor for optimal performan |
April 29, 2008 |
| A coprocessor executing one among a set of candidate kernel loops within an application operates at the minimal clock frequency satisfying schedule constraints imposed by the compiler and data bandwidth constraints. The optimal clock frequency is statically determined by the compiler |
| 7365928 |
Write driver with improved boosting circuit and interconnect impedance matching |
April 29, 2008 |
| A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in |
| 7362248 |
Temperature tamper detection circuit and method |
April 22, 2008 |
| A sensing circuit determines whether an integrated circuit is currently exposed to one of a relatively low or a relatively high temperature. A selection circuit selects a measured voltage across the base-emitter of a bipolar transistor if the sensing circuit indicates that the circuit is |
| 7358628 |
Configurable circuit and method for detecting the state of a switch |
April 15, 2008 |
| A circuit and method are disclosed for monitoring the state of at least one switch. The circuit may include a first circuit, coupled to a switch, for detecting whether the switch is in one of a closed state and an open state and generating a signal having a value based upon the detection |
| 7355303 |
Constant voltage discharge device |
April 8, 2008 |
| Circuits and methods for supplying a temporary power supply at a predetermined voltage. A circuit includes a first DC/DC voltage converter that receives an input from a power supply at a first voltage level and generates an output at a second voltage level, higher than the first volt |
| 7353706 |
Weighted released-beam sensor |
April 8, 2008 |
| A released-beam sensor includes a semiconductor substrate having a layer formed thereon, and an aperture formed in the layer. A beam is mechanically coupled at a first end to the layer and suspended above the layer such that a second end forms a cantilever above the aperture. A boss |
| 7346836 |
E.sup.2PR4 viterbi detector and method for adding a branch metric to the path metric of the surv |
March 18, 2008 |
| An E.sup.2PR4 Viterbi detector receives a signal that represents a sequence of values, the sequence having a potential state. The detector includes a recovery circuit that recovers the sequence from the signal by identifying the surviving path to the potential state and simultaneously |
| 7339204 |
Backside contact for touchchip |
March 4, 2008 |
| A contact is formed within an active region of a substrate at the edge of a die, preferably within the first metallization level in the active region of the substrate. An opening having sloped sidewalls is then etched into the back side of the substrate, exposing a portion of the act |
| 7337419 |
Crosstalk noise reduction circuit and method |
February 26, 2008 |
| In a semiconductor device, a method for reducing the effect of crosstalk from an aggressor line to a victim line begins with sensing the occurrence of a voltage change on the aggressor line that can induce a voltage pulse having a pulse magnitude that exceeds a pulse threshold on the |
| 7337306 |
Executing conditional branch instructions in a data processor having a clustered architecture |
February 26, 2008 |
| There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the br |
| 7337253 |
Method and system of routing network-based data using frame address notification |
February 26, 2008 |
| A method and system for routing network-based data arranged in frames is disclosed. A host processor analyzes transferred bursts of data and initiates an address and look up algorithm for dispatching the frame to a desired destination. A shared system memory existing between a network |
| 7336517 |
Physical priority encoder |
February 26, 2008 |
| A priority encoder can be used for a Content-Addressable Memory (CAM) device that typically has an array of CAM cells arranged in columns and rows with each row having a match signal indicative that compare data has matched data within the respective row. A priority encoder is operativel |
| 7333310 |
ESD bonding pad |
February 19, 2008 |
| A bonding pad arrangement for an integrated circuit includes a bonding pad fabricated on a bonding area to enable bonding. A first ESD resistor is fabricated adjacent the bonding area, and at least a second ESD resistor is fabricated adjacent the first ESD resistor and the bonding area. |
