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STMicroelectronics, Inc. Patents
Assignee:
STMicroelectronics, Inc.
Address:
Coppell, TX
No. of patents:
1134
Patents:












Patent Number Title Of Patent Date Issued
RE42250 Delay circuit and method March 29, 2011
A reduced area delay circuit and method are disclosed. The delay circuit uses a constant current source and a constant current drain to charge and discharge a capacitor and thus control the delay time of the delay circuit. The constant current source and drain can be implemented using
RE41728 High linearity, low power voltage controlled resistor September 21, 2010
A number of voltage-controlled resistance cells, each formed by a transistor with a biasing capacitor connected between the gate and source and an associated controller coupled to the capacitor to maintain a steady charge on the biasing capacitor and keep the gate-source voltage at a
RE41670 Sram cell fabrication with interlevel Dielectric planarization September 14, 2010
A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.
RE41337 Synchronous test mode initialization May 18, 2010
The entire data path of a synchronous integrated circuit device is initialized in a test mode upon power-up of the synchronous integrated circuit device. Upon power-up of the integrated circuit device in the test mode, a clock signal (either an external clock signal or an associated
RE41068 Spacer-type thin-film polysilicon transistor for low-power memory devices January 5, 2010
The cross-sectional area of a thin-film transistor (TFT) is decreased in order to minimize bitline to supply leakage of the TFT. This is accomplished by utilizing a spacer etch process to manufacture a TFT having a very narrow and thin channel in a controllable manner. The spacer dim
RE40579 Structure for transistor devices in an SRAM cell November 25, 2008
An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate tran
RE40282 Edge transition detection circuitry for use with test mode operation of an integrated circuit me April 29, 2008
An integrated circuit structure and method provides for an integrated circuit device to respond to an edge transition detection (ETD) pulse in one of two ways. First, in response to the ETD pulse, the integrated circuit device exits a test mode at least temporarily every cycle of the
RE39918 Direct current sum bandgap voltage comparator November 13, 2007
A direct current sum bandgap voltage comparator for detecting voltage changes in a power supply. The direct current sum bandgap voltage comparator includes a summing node, current sources connected to the summing node and the power supply, and an indicator circuit connected to the su
RE39690 Enhanced planarization technique for an integrated circuit June 12, 2007
A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.
RE38891 Programmable load transient compensator for reducing the transient response time to a load capab November 22, 2005
A load transient compensator and method of operating the load transient compensator for reducing the transient response time to a load .[.capable of operating at either of several consumption levels when the load changes its power consumption level.]. . The load transient compensator has
RE38250 Bandgap reference circuit September 16, 2003
According to the present invention, a circuit, utilizing a minimum number of bipolar devices and current mirror scaling devices, generates a bandgap reference voltage. The bandgap voltage generated by the bandgap reference circuit is a function of a plurality of sized current mirror devi
RE38045 Data compensation/resynchronization circuit for phase lock loops March 25, 2003
A circuit that compensates for delays induced by clock generation logic and distributed clock drivers in phase lock loop applications is disclosed. The circuit is a phase lock loop (PLL) which contains a clock synchronization circuit that operates to synchronize a transition edge of
RE37876 Power supply switch reference circuitry October 15, 2002
An apparatus and method for switching between two power supplies, a primary power supply and a secondary power supply. The present invention generates a first reference voltage using the voltage of the primary power supply and the secondary power supply, wherein the primary power supply
RE37769 Methods for fabricating memory cells and load elements June 25, 2002
A contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the
RE37708 Programmable bandwidth voltage regulator May 21, 2002
A method for reducing the transient response time of a voltage regulator when the load attached to it is entering or exiting a lower power consumption level by changing the bandwidth of the voltage regulator without compromising its stability, and a bandwidth regulator for implementi
RE37082 RF transistor package with nickel oxide barrier March 6, 2001
An improved transistor package with superior stability to wave soldering, having a nickel oxide barrier strip formed on the surface of the leads.
RE36938 Method of forming a landing pad structure in an integrated circuit October 31, 2000
A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is
RE36319 Structure for deselective broken select lines in memory arrays September 28, 1999
According to the present invention, a structure for holding broken select lines in a memory array deselected addresses the prior art problems associated with floating broken select lines, such as standby current and disruption of attached memory cells. The structure is a high impedance
RE36292 Operational analysis device of the scan path type having a single scanning clock and a single ou September 7, 1999
The device comprises a first chain of scanning cells located at the stimulation input of each respective functional block of the integrated circuit and a second chain of scanning cells located at the assessment output of each respective functional block of the integrated circuit. Each
8583836 Packet-based digital display interface signal mapping to bi-directional serial interface signals November 12, 2013
A passive cable adaptor for connecting a data source device with a display device is described. The adaptor has a packet-based interface connector at one end, the connector having a positive main link pin, a negative main link pin, a positive auxiliary channel pin, and a negative aux
8582452 Data link configuration by a receiver in the absence of link training data November 12, 2013
A receiver is enabled to perform self-configuration of the main data link to receive and display video data. A video data signal is received through a data link having multiple channels or lanes at a specific bit rate. No link configuration data normally associated with the video sig
8578031 Packet-based digital display interface signal mapping to micro serial interface November 5, 2013
A passive cable adaptor for connecting a data source device with a display device is described. The adaptor has a packet-based interface connector at one end, the connector having a positive main link pin, a negative main link pin, a positive auxiliary channel pin, and a negative aux
8576341 Occlusion adaptive motion compensated interpolator November 5, 2013
In one embodiment of the present invention, motion compensated interpolation is performed by locating full frame conceal and reveal areas, determining intermediate frame occlusion areas of an interpolated frame of the displayable output by locating intermediate frame conceal areas ba
8571026 System and method for an intelligent load center with integrated powerline communications networ October 29, 2013
In a typical powerline communications environment, all electrical outlets and branches are connected to a load center. In this type of electrical system, all communication devices will share the same frequency spectrum, limiting the maximum bandwidth of the network, where all nodes are i
8569899 Device and method for alignment of vertically stacked wafers and die October 29, 2013
A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality o
8569809 Organic semiconductor sensor device October 29, 2013
Sensor cells are arranged in an array in an organic semiconductor layer. Row and column select circuitry addresses the cells of the array one cell at a time to determine the presence of an object, such as a fingerprint ridge or valley, contacting or proximate to a sensing surface above e
8566828 Accelerator for multi-processing system and method October 22, 2013
A processing system includes a plurality of processors capable of executing a plurality of threads and supporting at least one of hardware context switching and software context switching. The processing system also includes a hardware concurrency engine coupled to the plurality of p
8565673 Hierarchical networks utilizing frame transmissions pipelining October 22, 2013
A hierarchical WRAN includes a relay station (RS) possessing dual roles. A RS acts from the perspective of a base station (BS) as a consumer premise equipment (CPE) terminal just as any other first tier CPE terminal. Simultaneously, the RS, from the perspective of other second tier C
8565062 Method and system of channel analysis and carrier selection in OFDM and multi-carrier systems October 22, 2013
The invention presents a novel method to channel estimation in OFDM systems. The embodiment of this invention is a block of new logic and modifications performed to other components of the system, added to any existing OFDM receiver, which utilizes information available from other bl
8564137 System for relieving stress and improving heat management in a 3D chip stack having an array of October 22, 2013
The present disclosure provides a system and method for relieving stress and providing improved heat management in a 3D chip stack of a multichip package. A stress relief apparatus is provided to allow the chip stack to adjust in response to pressure, thereby relieving stress applied to
8295286 Apparatus and method using hashing for efficiently implementing an IP lookup solution in hardwar October 23, 2012
Internet Protocol address prefixes are hashed into hash tables allocated memory blocks on demand after collisions occur for both a first hash and a single rehash. The number of memory blocks allocated to each hash table is limited, with additional prefixes handled by an overflow content
8291207 Frequency and symbol locking using signal generated clock frequency and symbol identification October 16, 2012
Methods and systems are described for displaying video data after a hot plug event during a start-up dead period. In particular, approaches for receiving data, determining whether link training can be performed and, if not, self-configuring a receiver to display the information in a
8290102 Adaptive data dependent noise prediction (ADDNP) October 16, 2012
A method is provided. The method comprises calibrating noise prediction parameters by adapting one or more biases, adapting one or more filter coefficients using the adapted one or more biases, and adapting one or more prediction error variances using the adapted one or more biases and
8289446 Intermediate frame occlusion estimation system using projected vectors October 16, 2012
In one embodiment, a method is provided for performing motion compensated interpolation wherein, for any pixels in the interpolated frame to which there is neither a forward vector nor a backward vector projecting: including the pixel in an intermediate frame conceal area if it is not
8285297 Fair channel use in a wireless area network October 9, 2012
Fair usage of working channels in a wireless network is disclosed. A base station associated with a cell within a wireless community monitors the congestion of the working channel of neighboring communities. Upon determining that the congestion of the working channel of a neighboring
8284775 Six-address scheme for multiple hop forwarding in wireless mesh networks October 9, 2012
A six field address scheme identifies both the originating point and the endpoint of a data frame enabling multiple hop forwarding through a plurality of intermediate mesh points in a wireless mesh network. Data frames originating or ending at a point outside of the wireless mesh net
8283769 Modular low stress package technology October 9, 2012
A protective modular package cover has first and second fastening sections located at opposing first and second ends with one or more subassembly receiving sections disposed thereto and is configured to fasten the protective modular package cover to a core. Each fastening section has
8275144 Intelligent audio speakers September 25, 2012
An intelligent audio speaker that uses a power line communication element to provide audio distribution within homes, businesses, apartment complexes, and other buildings. Multiple intelligent audio speakers may be networked together, with common control. The intelligent audio speaker
8270585 System and method for an endpoint participating in and managing multipoint audio conferencing in September 18, 2012
A system and method is disclosed for implementing a multipoint control unit in an endpoint that is participating in and managing a multipoint audio conference in a packet network. The multipoint control unit establishes audio communications between a plurality of endpoints of the pac
8270302 System and method for providing an adaptive value of TTL (time to live) for broadcast/multicast September 18, 2012
A system and method is disclosed for providing an adaptive value of a TTL (Time to Live) count for broadcast/multicast messages in a wireless mesh network using a hybrid wireless mesh protocol. A mesh point controller is provided that adaptively selects the value of the TTL count and rou
8264541 Compound camera and methods for implementing auto-focus, depth-of-field and high-resolution func September 11, 2012
A compound camera system for generating an enhanced virtual image having a large depth-of-field. The compound camera system comprises a plurality of component cameras for generating image data of an object and a data processor for generating the enhanced virtual image from the image data
8259760 Apparatus and method for transmitting and recovering multi-lane encoded data streams using a red September 4, 2012
A method includes receiving first encoded data associated with one or more first lanes and decoding the first encoded data to produce decoded data. The method also includes encoding the decoded data to produce second encoded data associated with one or more second lanes and transmitt
8255768 Interlaced iterative system design for 1K-byte block with 512-byte LDPC codewords August 28, 2012
To allow a single LDPC decoder to operate on both 512 B blocks and 4 KB blocks with comparable error correction performance, 512 KB blocks are interlaced to form a 1 KB data sequence, and four sequential 1 KB data sequences are concatenated to form a 4 KB sector. A de-interlacer between
8254922 Zero delay frequency switching with dynamic frequency hopping for cognitive radio based dynamic August 28, 2012
This invention relates to cognitive radio based wireless communications of dynamic spectrum access networks, and in particular to a method of addressing zero-delay frequency switching for cognitive dynamic frequency hopping. The method combines regular (periodic) channel maintenance with
8249033 Communication between overlapping WRAN cells working in different channels August 21, 2012
A common control channel for base station ("BS")/consumer premise equipment ("CPE") communication in areas of overlapping coverage by wireless regional area network ("WRAN") cells operating on different working channels is disclosed. A common control channel is selected from among th
8248325 Drive circuit August 21, 2012
A plurality of resistive paths are coupled in parallel to a common node. A high side driver is operable responsive to first control signals to selectively supply current to certain ones of the resistive paths. A low side driver, including a plurality of selectively actuated current sink
8242876 Dual thin film precision resistance trimming August 14, 2012
A trimmable resistor for use in an integrated circuit is trimmed using a heater. The heater is selectively coupled to a voltage source. The application of voltage to the heater causes the heater temperature to increase and produce heat. The heat permeates through a thermal separator
8242748 Trailer tow preserving battery charge circuit August 14, 2012
A method and integrated circuit for preserving a battery's charge and protecting electrical devices is disclosed. A maximum and a minimum battery voltage value at the output port are stored in a memory. A steady state battery voltage at the output port is measured and stored in the m
8239660 Processor with automatic scheduling of operations August 7, 2012
A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A notation is made when
8239592 Smart card with self-detachment features and related methods August 7, 2012
An integrated circuit for a smart card in accordance with an exemplary embodiment includes at least one data terminal for providing communications with a host device over a system bus and a processor configured to provide an attachment signal on the at least one data terminal for rec

 
 
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