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SK hynix memory solutions inc. Patents
SK hynix memory solutions inc.
San Jose, CA
No. of patents:

Patent Number Title Of Patent Date Issued
8589760 Defect scan and manufacture test November 19, 2013
A method for detecting a defect in a portion of a storage device is disclosed. Reference data and data read from the portion are compared to determine a number of error bits and a number of error symbols. An error ratio is computed, wherein the error ratio comprises a ratio of the nu
8583979 Multiple interleavers in a coding system November 12, 2013
A technique for processing data. The technique includes modulation encoding input data. A first interleaving process is used to obtain first interleaved data. The first interleaved data is systematically encoded. The systematically encoded data is interleaved using a second interleav
8572471 SOVA sharing during LDPC global iteration October 29, 2013
Decoding is performed on input data to obtain first decoded data using a first error correction decoder. If decoding by a second error correction decoder on the first decoded data fails, decoding is performed using an output of the second decoder and using the first decoder. A reservatio
8572463 Quasi-cyclic LDPC encoding and decoding for non-integer multiples of circulant size October 29, 2013
In processing quasi-cyclic low-density parity-check (QC-LDPC) data, an input signal is received which includes decision and reliability information corresponding to unpadded data. Decision and reliability information corresponding to padded data is introduced into the input signal. M
8570879 Obtaining parameters for minimizing an error event probability October 29, 2013
A set of one or more receiver parameters is adjusted. It is determined whether to adjust the set of receiver parameters. In the event it is determined to adjust the set of receiver parameters, a new set of values is generated for the set of receiver parameters using a cost function (
8570680 Pad bit injection during read operation to improve format efficiency October 29, 2013
Injecting pad bits during a read operation to improve format efficiency is disclosed. In some embodiments, a pad sequence associated with error correction is not stored in a sector on a disk. Instead, the pad sequence is merged at a read channel with data stored in a sector that is acces

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